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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2105 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard 2006-08-09 22:38:19 +00:00
parent 35b961cf8d
commit 2a98c1981f
1 changed files with 176 additions and 176 deletions
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352
hw/lance.c
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@ -48,55 +48,55 @@ do { printf("LANCE: " fmt , ##args); } while (0)
#define LE_RDP 0 #define LE_RDP 0
#define LE_RAP 1 #define LE_RAP 1
#define LE_MO_PROM 0x8000 /* Enable promiscuous mode */ #define LE_MO_PROM 0x8000 /* Enable promiscuous mode */
#define LE_C0_ERR 0x8000 /* Error: set if BAB, SQE, MISS or ME is set */ #define LE_C0_ERR 0x8000 /* Error: set if BAB, SQE, MISS or ME is set */
#define LE_C0_BABL 0x4000 /* BAB: Babble: tx timeout. */ #define LE_C0_BABL 0x4000 /* BAB: Babble: tx timeout. */
#define LE_C0_CERR 0x2000 /* SQE: Signal quality error */ #define LE_C0_CERR 0x2000 /* SQE: Signal quality error */
#define LE_C0_MISS 0x1000 /* MISS: Missed a packet */ #define LE_C0_MISS 0x1000 /* MISS: Missed a packet */
#define LE_C0_MERR 0x0800 /* ME: Memory error */ #define LE_C0_MERR 0x0800 /* ME: Memory error */
#define LE_C0_RINT 0x0400 /* Received interrupt */ #define LE_C0_RINT 0x0400 /* Received interrupt */
#define LE_C0_TINT 0x0200 /* Transmitter Interrupt */ #define LE_C0_TINT 0x0200 /* Transmitter Interrupt */
#define LE_C0_IDON 0x0100 /* IFIN: Init finished. */ #define LE_C0_IDON 0x0100 /* IFIN: Init finished. */
#define LE_C0_INTR 0x0080 /* Interrupt or error */ #define LE_C0_INTR 0x0080 /* Interrupt or error */
#define LE_C0_INEA 0x0040 /* Interrupt enable */ #define LE_C0_INEA 0x0040 /* Interrupt enable */
#define LE_C0_RXON 0x0020 /* Receiver on */ #define LE_C0_RXON 0x0020 /* Receiver on */
#define LE_C0_TXON 0x0010 /* Transmitter on */ #define LE_C0_TXON 0x0010 /* Transmitter on */
#define LE_C0_TDMD 0x0008 /* Transmitter demand */ #define LE_C0_TDMD 0x0008 /* Transmitter demand */
#define LE_C0_STOP 0x0004 /* Stop the card */ #define LE_C0_STOP 0x0004 /* Stop the card */
#define LE_C0_STRT 0x0002 /* Start the card */ #define LE_C0_STRT 0x0002 /* Start the card */
#define LE_C0_INIT 0x0001 /* Init the card */ #define LE_C0_INIT 0x0001 /* Init the card */
#define LE_C3_BSWP 0x4 /* SWAP */ #define LE_C3_BSWP 0x4 /* SWAP */
#define LE_C3_ACON 0x2 /* ALE Control */ #define LE_C3_ACON 0x2 /* ALE Control */
#define LE_C3_BCON 0x1 /* Byte control */ #define LE_C3_BCON 0x1 /* Byte control */
/* Receive message descriptor 1 */ /* Receive message descriptor 1 */
#define LE_R1_OWN 0x80 /* Who owns the entry */ #define LE_R1_OWN 0x80 /* Who owns the entry */
#define LE_R1_ERR 0x40 /* Error: if FRA, OFL, CRC or BUF is set */ #define LE_R1_ERR 0x40 /* Error: if FRA, OFL, CRC or BUF is set */
#define LE_R1_FRA 0x20 /* FRA: Frame error */ #define LE_R1_FRA 0x20 /* FRA: Frame error */
#define LE_R1_OFL 0x10 /* OFL: Frame overflow */ #define LE_R1_OFL 0x10 /* OFL: Frame overflow */
#define LE_R1_CRC 0x08 /* CRC error */ #define LE_R1_CRC 0x08 /* CRC error */
#define LE_R1_BUF 0x04 /* BUF: Buffer error */ #define LE_R1_BUF 0x04 /* BUF: Buffer error */
#define LE_R1_SOP 0x02 /* Start of packet */ #define LE_R1_SOP 0x02 /* Start of packet */
#define LE_R1_EOP 0x01 /* End of packet */ #define LE_R1_EOP 0x01 /* End of packet */
#define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */ #define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */
#define LE_T1_OWN 0x80 /* Lance owns the packet */ #define LE_T1_OWN 0x80 /* Lance owns the packet */
#define LE_T1_ERR 0x40 /* Error summary */ #define LE_T1_ERR 0x40 /* Error summary */
#define LE_T1_EMORE 0x10 /* Error: more than one retry needed */ #define LE_T1_EMORE 0x10 /* Error: more than one retry needed */
#define LE_T1_EONE 0x08 /* Error: one retry needed */ #define LE_T1_EONE 0x08 /* Error: one retry needed */
#define LE_T1_EDEF 0x04 /* Error: deferred */ #define LE_T1_EDEF 0x04 /* Error: deferred */
#define LE_T1_SOP 0x02 /* Start of packet */ #define LE_T1_SOP 0x02 /* Start of packet */
#define LE_T1_EOP 0x01 /* End of packet */ #define LE_T1_EOP 0x01 /* End of packet */
#define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */ #define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */
#define LE_T3_BUF 0x8000 /* Buffer error */ #define LE_T3_BUF 0x8000 /* Buffer error */
#define LE_T3_UFL 0x4000 /* Error underflow */ #define LE_T3_UFL 0x4000 /* Error underflow */
#define LE_T3_LCOL 0x1000 /* Error late collision */ #define LE_T3_LCOL 0x1000 /* Error late collision */
#define LE_T3_CLOS 0x0800 /* Error carrier loss */ #define LE_T3_CLOS 0x0800 /* Error carrier loss */
#define LE_T3_RTY 0x0400 /* Error retry */ #define LE_T3_RTY 0x0400 /* Error retry */
#define LE_T3_TDR 0x03ff /* Time Domain Reflectometry counter */ #define LE_T3_TDR 0x03ff /* Time Domain Reflectometry counter */
#define TX_RING_SIZE (1 << (LANCE_LOG_TX_BUFFERS)) #define TX_RING_SIZE (1 << (LANCE_LOG_TX_BUFFERS))
#define TX_RING_MOD_MASK (TX_RING_SIZE - 1) #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
@ -111,42 +111,42 @@ do { printf("LANCE: " fmt , ##args); } while (0)
#define TX_BUFF_SIZE PKT_BUF_SZ #define TX_BUFF_SIZE PKT_BUF_SZ
struct lance_rx_desc { struct lance_rx_desc {
unsigned short rmd0; /* low address of packet */ unsigned short rmd0; /* low address of packet */
unsigned char rmd1_bits; /* descriptor bits */ unsigned char rmd1_bits; /* descriptor bits */
unsigned char rmd1_hadr; /* high address of packet */ unsigned char rmd1_hadr; /* high address of packet */
short length; /* This length is 2s complement (negative)! short length; /* This length is 2s complement (negative)!
* Buffer length * Buffer length
*/ */
unsigned short mblength; /* This is the actual number of bytes received */ unsigned short mblength; /* This is the actual number of bytes received */
}; };
struct lance_tx_desc { struct lance_tx_desc {
unsigned short tmd0; /* low address of packet */ unsigned short tmd0; /* low address of packet */
unsigned char tmd1_bits; /* descriptor bits */ unsigned char tmd1_bits; /* descriptor bits */
unsigned char tmd1_hadr; /* high address of packet */ unsigned char tmd1_hadr; /* high address of packet */
short length; /* Length is 2s complement (negative)! */ short length; /* Length is 2s complement (negative)! */
unsigned short misc; unsigned short misc;
}; };
/* The LANCE initialization block, described in databook. */ /* The LANCE initialization block, described in databook. */
/* On the Sparc, this block should be on a DMA region */ /* On the Sparc, this block should be on a DMA region */
struct lance_init_block { struct lance_init_block {
unsigned short mode; /* Pre-set mode (reg. 15) */ unsigned short mode; /* Pre-set mode (reg. 15) */
unsigned char phys_addr[6]; /* Physical ethernet address */ unsigned char phys_addr[6]; /* Physical ethernet address */
unsigned filter[2]; /* Multicast filter. */ unsigned filter[2]; /* Multicast filter. */
/* Receive and transmit ring base, along with extra bits. */ /* Receive and transmit ring base, along with extra bits. */
unsigned short rx_ptr; /* receive descriptor addr */ unsigned short rx_ptr; /* receive descriptor addr */
unsigned short rx_len; /* receive len and high addr */ unsigned short rx_len; /* receive len and high addr */
unsigned short tx_ptr; /* transmit descriptor addr */ unsigned short tx_ptr; /* transmit descriptor addr */
unsigned short tx_len; /* transmit len and high addr */ unsigned short tx_len; /* transmit len and high addr */
/* The Tx and Rx ring entries must aligned on 8-byte boundaries. */ /* The Tx and Rx ring entries must aligned on 8-byte boundaries. */
struct lance_rx_desc brx_ring[RX_RING_SIZE]; struct lance_rx_desc brx_ring[RX_RING_SIZE];
struct lance_tx_desc btx_ring[TX_RING_SIZE]; struct lance_tx_desc btx_ring[TX_RING_SIZE];
char tx_buf[TX_RING_SIZE][TX_BUFF_SIZE]; char tx_buf[TX_RING_SIZE][TX_BUFF_SIZE];
char pad[2]; /* align rx_buf for copy_and_sum(). */ char pad[2]; /* align rx_buf for copy_and_sum(). */
char rx_buf[RX_RING_SIZE][RX_BUFF_SIZE]; char rx_buf[RX_RING_SIZE][RX_BUFF_SIZE];
}; };
@ -155,11 +155,11 @@ struct lance_init_block {
typedef struct LANCEState { typedef struct LANCEState {
VLANClientState *vc; VLANClientState *vc;
uint8_t macaddr[6]; /* init mac address */ uint8_t macaddr[6]; /* init mac address */
uint32_t leptr; uint32_t leptr;
uint16_t addr; uint16_t addr;
uint16_t regs[LE_NREGS]; uint16_t regs[LE_NREGS];
uint8_t phys[6]; /* mac address */ uint8_t phys[6]; /* mac address */
int irq; int irq;
unsigned int rxptr, txptr; unsigned int rxptr, txptr;
uint32_t ledmaregs[LEDMA_REGS]; uint32_t ledmaregs[LEDMA_REGS];
@ -186,20 +186,20 @@ static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)
saddr = addr & LE_MAXREG; saddr = addr & LE_MAXREG;
switch (saddr >> 1) { switch (saddr >> 1) {
case LE_RDP: case LE_RDP:
DPRINTF("read dreg[%d] = %4.4x\n", s->addr, s->regs[s->addr]); DPRINTF("read dreg[%d] = %4.4x\n", s->addr, s->regs[s->addr]);
return s->regs[s->addr]; return s->regs[s->addr];
case LE_RAP: case LE_RAP:
DPRINTF("read areg = %4.4x\n", s->addr); DPRINTF("read areg = %4.4x\n", s->addr);
return s->addr; return s->addr;
default: default:
DPRINTF("read unknown(%d)\n", saddr >> 1); DPRINTF("read unknown(%d)\n", saddr >> 1);
break; break;
} }
return 0; return 0;
} }
static void lance_mem_writew(void *opaque, target_phys_addr_t addr, static void lance_mem_writew(void *opaque, target_phys_addr_t addr,
uint32_t val) uint32_t val)
{ {
LANCEState *s = opaque; LANCEState *s = opaque;
uint32_t saddr; uint32_t saddr;
@ -208,62 +208,62 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr,
saddr = addr & LE_MAXREG; saddr = addr & LE_MAXREG;
switch (saddr >> 1) { switch (saddr >> 1) {
case LE_RDP: case LE_RDP:
DPRINTF("write dreg[%d] = %4.4x\n", s->addr, val); DPRINTF("write dreg[%d] = %4.4x\n", s->addr, val);
switch (s->addr) { switch (s->addr) {
case LE_CSR0: case LE_CSR0:
if (val & LE_C0_STOP) { if (val & LE_C0_STOP) {
s->regs[LE_CSR0] = LE_C0_STOP; s->regs[LE_CSR0] = LE_C0_STOP;
break; break;
} }
reg = s->regs[LE_CSR0]; reg = s->regs[LE_CSR0];
// 1 = clear for some bits // 1 = clear for some bits
reg &= ~(val & 0x7f00); reg &= ~(val & 0x7f00);
// generated bits // generated bits
reg &= ~(LE_C0_ERR | LE_C0_INTR); reg &= ~(LE_C0_ERR | LE_C0_INTR);
if (reg & 0x7100) if (reg & 0x7100)
reg |= LE_C0_ERR; reg |= LE_C0_ERR;
if (reg & 0x7f00) if (reg & 0x7f00)
reg |= LE_C0_INTR; reg |= LE_C0_INTR;
// direct bit // direct bit
reg &= ~LE_C0_INEA; reg &= ~LE_C0_INEA;
reg |= val & LE_C0_INEA; reg |= val & LE_C0_INEA;
// exclusive bits // exclusive bits
if (val & LE_C0_INIT) { if (val & LE_C0_INIT) {
reg |= LE_C0_IDON | LE_C0_INIT; reg |= LE_C0_IDON | LE_C0_INIT;
reg &= ~LE_C0_STOP; reg &= ~LE_C0_STOP;
} else if (val & LE_C0_STRT) { } else if (val & LE_C0_STRT) {
reg |= LE_C0_STRT | LE_C0_RXON | LE_C0_TXON; reg |= LE_C0_STRT | LE_C0_RXON | LE_C0_TXON;
reg &= ~LE_C0_STOP; reg &= ~LE_C0_STOP;
} }
s->regs[LE_CSR0] = reg; s->regs[LE_CSR0] = reg;
break; break;
case LE_CSR1: case LE_CSR1:
s->leptr = (s->leptr & 0xffff0000) | (val & 0xffff); s->leptr = (s->leptr & 0xffff0000) | (val & 0xffff);
s->regs[s->addr] = val; s->regs[s->addr] = val;
break; break;
case LE_CSR2: case LE_CSR2:
s->leptr = (s->leptr & 0xffff) | ((val & 0xffff) << 16); s->leptr = (s->leptr & 0xffff) | ((val & 0xffff) << 16);
s->regs[s->addr] = val; s->regs[s->addr] = val;
break; break;
case LE_CSR3: case LE_CSR3:
s->regs[s->addr] = val; s->regs[s->addr] = val;
break; break;
} }
break; break;
case LE_RAP: case LE_RAP:
DPRINTF("write areg = %4.4x\n", val); DPRINTF("write areg = %4.4x\n", val);
if (val < LE_NREGS) if (val < LE_NREGS)
s->addr = val; s->addr = val;
break; break;
default: default:
DPRINTF("write unknown(%d) = %4.4x\n", saddr >> 1, val); DPRINTF("write unknown(%d) = %4.4x\n", saddr >> 1, val);
break; break;
} }
lance_send(s); lance_send(s);
} }
@ -299,32 +299,32 @@ static void lance_receive(void *opaque, const uint8_t * buf, int size)
DPRINTF("receive size %d\n", size); DPRINTF("receive size %d\n", size);
if ((s->regs[LE_CSR0] & LE_C0_STOP) == LE_C0_STOP) if ((s->regs[LE_CSR0] & LE_C0_STOP) == LE_C0_STOP)
return; return;
ib = (void *) iommu_translate(dmaptr); ib = (void *) iommu_translate(dmaptr);
old_rxptr = s->rxptr; old_rxptr = s->rxptr;
for (i = s->rxptr; i != ((old_rxptr - 1) & RX_RING_MOD_MASK); for (i = s->rxptr; i != ((old_rxptr - 1) & RX_RING_MOD_MASK);
i = (i + 1) & RX_RING_MOD_MASK) { i = (i + 1) & RX_RING_MOD_MASK) {
cpu_physical_memory_read((uint32_t) & ib->brx_ring[i].rmd1_bits, cpu_physical_memory_read((uint32_t) & ib->brx_ring[i].rmd1_bits,
(void *) &temp8, 1); (void *) &temp8, 1);
if (temp8 == (LE_R1_OWN)) { if (temp8 == (LE_R1_OWN)) {
s->rxptr = (s->rxptr + 1) & RX_RING_MOD_MASK; s->rxptr = (s->rxptr + 1) & RX_RING_MOD_MASK;
temp16 = size + 4; temp16 = size + 4;
bswap16s(&temp16); bswap16s(&temp16);
cpu_physical_memory_write((uint32_t) & ib->brx_ring[i]. cpu_physical_memory_write((uint32_t) & ib->brx_ring[i].
mblength, (void *) &temp16, 2); mblength, (void *) &temp16, 2);
cpu_physical_memory_write((uint32_t) & ib->rx_buf[i], buf, cpu_physical_memory_write((uint32_t) & ib->rx_buf[i], buf,
size); size);
temp8 = LE_R1_POK; temp8 = LE_R1_POK;
cpu_physical_memory_write((uint32_t) & ib->brx_ring[i]. cpu_physical_memory_write((uint32_t) & ib->brx_ring[i].
rmd1_bits, (void *) &temp8, 1); rmd1_bits, (void *) &temp8, 1);
s->regs[LE_CSR0] |= LE_C0_RINT | LE_C0_INTR; s->regs[LE_CSR0] |= LE_C0_RINT | LE_C0_INTR;
if (s->regs[LE_CSR0] & LE_C0_INEA) if (s->regs[LE_CSR0] & LE_C0_INEA)
pic_set_irq(s->irq, 1); pic_set_irq(s->irq, 1);
DPRINTF("got packet, len %d\n", size); DPRINTF("got packet, len %d\n", size);
return; return;
} }
} }
} }
@ -340,35 +340,35 @@ static void lance_send(void *opaque)
DPRINTF("sending packet? (csr0 %4.4x)\n", s->regs[LE_CSR0]); DPRINTF("sending packet? (csr0 %4.4x)\n", s->regs[LE_CSR0]);
if ((s->regs[LE_CSR0] & LE_C0_STOP) == LE_C0_STOP) if ((s->regs[LE_CSR0] & LE_C0_STOP) == LE_C0_STOP)
return; return;
ib = (void *) iommu_translate(dmaptr); ib = (void *) iommu_translate(dmaptr);
DPRINTF("sending packet? (dmaptr %8.8x) (ib %p) (btx_ring %p)\n", DPRINTF("sending packet? (dmaptr %8.8x) (ib %p) (btx_ring %p)\n",
dmaptr, ib, &ib->btx_ring); dmaptr, ib, &ib->btx_ring);
old_txptr = s->txptr; old_txptr = s->txptr;
for (i = s->txptr; i != ((old_txptr - 1) & TX_RING_MOD_MASK); for (i = s->txptr; i != ((old_txptr - 1) & TX_RING_MOD_MASK);
i = (i + 1) & TX_RING_MOD_MASK) { i = (i + 1) & TX_RING_MOD_MASK) {
cpu_physical_memory_read((uint32_t) & ib->btx_ring[i].tmd1_bits, cpu_physical_memory_read((uint32_t) & ib->btx_ring[i].tmd1_bits,
(void *) &temp8, 1); (void *) &temp8, 1);
if (temp8 == (LE_T1_POK | LE_T1_OWN)) { if (temp8 == (LE_T1_POK | LE_T1_OWN)) {
cpu_physical_memory_read((uint32_t) & ib->btx_ring[i].length, cpu_physical_memory_read((uint32_t) & ib->btx_ring[i].length,
(void *) &temp16, 2); (void *) &temp16, 2);
bswap16s(&temp16); bswap16s(&temp16);
temp16 = (~temp16) + 1; temp16 = (~temp16) + 1;
cpu_physical_memory_read((uint32_t) & ib->tx_buf[i], pkt_buf, cpu_physical_memory_read((uint32_t) & ib->tx_buf[i], pkt_buf,
temp16); temp16);
DPRINTF("sending packet, len %d\n", temp16); DPRINTF("sending packet, len %d\n", temp16);
qemu_send_packet(s->vc, pkt_buf, temp16); qemu_send_packet(s->vc, pkt_buf, temp16);
temp8 = LE_T1_POK; temp8 = LE_T1_POK;
cpu_physical_memory_write((uint32_t) & ib->btx_ring[i]. cpu_physical_memory_write((uint32_t) & ib->btx_ring[i].
tmd1_bits, (void *) &temp8, 1); tmd1_bits, (void *) &temp8, 1);
s->txptr = (s->txptr + 1) & TX_RING_MOD_MASK; s->txptr = (s->txptr + 1) & TX_RING_MOD_MASK;
s->regs[LE_CSR0] |= LE_C0_TINT | LE_C0_INTR; s->regs[LE_CSR0] |= LE_C0_TINT | LE_C0_INTR;
} }
} }
if ((s->regs[LE_CSR0] & LE_C0_INTR) && (s->regs[LE_CSR0] & LE_C0_INEA)) if ((s->regs[LE_CSR0] & LE_C0_INTR) && (s->regs[LE_CSR0] & LE_C0_INEA))
pic_set_irq(s->irq, 1); pic_set_irq(s->irq, 1);
} }
static uint32_t ledma_mem_readl(void *opaque, target_phys_addr_t addr) static uint32_t ledma_mem_readl(void *opaque, target_phys_addr_t addr)
@ -381,7 +381,7 @@ static uint32_t ledma_mem_readl(void *opaque, target_phys_addr_t addr)
} }
static void ledma_mem_writel(void *opaque, target_phys_addr_t addr, static void ledma_mem_writel(void *opaque, target_phys_addr_t addr,
uint32_t val) uint32_t val)
{ {
LANCEState *s = opaque; LANCEState *s = opaque;
uint32_t saddr; uint32_t saddr;
@ -410,11 +410,11 @@ static void lance_save(QEMUFile * f, void *opaque)
qemu_put_be32s(f, &s->leptr); qemu_put_be32s(f, &s->leptr);
qemu_put_be16s(f, &s->addr); qemu_put_be16s(f, &s->addr);
for (i = 0; i < LE_NREGS; i++) for (i = 0; i < LE_NREGS; i++)
qemu_put_be16s(f, &s->regs[i]); qemu_put_be16s(f, &s->regs[i]);
qemu_put_buffer(f, s->phys, 6); qemu_put_buffer(f, s->phys, 6);
qemu_put_be32s(f, &s->irq); qemu_put_be32s(f, &s->irq);
for (i = 0; i < LEDMA_REGS; i++) for (i = 0; i < LEDMA_REGS; i++)
qemu_put_be32s(f, &s->ledmaregs[i]); qemu_put_be32s(f, &s->ledmaregs[i]);
} }
static int lance_load(QEMUFile * f, void *opaque, int version_id) static int lance_load(QEMUFile * f, void *opaque, int version_id)
@ -423,16 +423,16 @@ static int lance_load(QEMUFile * f, void *opaque, int version_id)
int i; int i;
if (version_id != 1) if (version_id != 1)
return -EINVAL; return -EINVAL;
qemu_get_be32s(f, &s->leptr); qemu_get_be32s(f, &s->leptr);
qemu_get_be16s(f, &s->addr); qemu_get_be16s(f, &s->addr);
for (i = 0; i < LE_NREGS; i++) for (i = 0; i < LE_NREGS; i++)
qemu_get_be16s(f, &s->regs[i]); qemu_get_be16s(f, &s->regs[i]);
qemu_get_buffer(f, s->phys, 6); qemu_get_buffer(f, s->phys, 6);
qemu_get_be32s(f, &s->irq); qemu_get_be32s(f, &s->irq);
for (i = 0; i < LEDMA_REGS; i++) for (i = 0; i < LEDMA_REGS; i++)
qemu_get_be32s(f, &s->ledmaregs[i]); qemu_get_be32s(f, &s->ledmaregs[i]);
return 0; return 0;
} }
@ -443,16 +443,16 @@ void lance_init(NICInfo * nd, int irq, uint32_t leaddr, uint32_t ledaddr)
s = qemu_mallocz(sizeof(LANCEState)); s = qemu_mallocz(sizeof(LANCEState));
if (!s) if (!s)
return; return;
s->irq = irq; s->irq = irq;
lance_io_memory = lance_io_memory =
cpu_register_io_memory(0, lance_mem_read, lance_mem_write, s); cpu_register_io_memory(0, lance_mem_read, lance_mem_write, s);
cpu_register_physical_memory(leaddr, 4, lance_io_memory); cpu_register_physical_memory(leaddr, 4, lance_io_memory);
ledma_io_memory = ledma_io_memory =
cpu_register_io_memory(0, ledma_mem_read, ledma_mem_write, s); cpu_register_io_memory(0, ledma_mem_read, ledma_mem_write, s);
cpu_register_physical_memory(ledaddr, 16, ledma_io_memory); cpu_register_physical_memory(ledaddr, 16, ledma_io_memory);
memcpy(s->macaddr, nd->macaddr, 6); memcpy(s->macaddr, nd->macaddr, 6);
@ -460,14 +460,14 @@ void lance_init(NICInfo * nd, int irq, uint32_t leaddr, uint32_t ledaddr)
lance_reset(s); lance_reset(s);
s->vc = s->vc =
qemu_new_vlan_client(nd->vlan, lance_receive, lance_can_receive, qemu_new_vlan_client(nd->vlan, lance_receive, lance_can_receive,
s); s);
snprintf(s->vc->info_str, sizeof(s->vc->info_str), snprintf(s->vc->info_str, sizeof(s->vc->info_str),
"lance macaddr=%02x:%02x:%02x:%02x:%02x:%02x", "lance macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
s->macaddr[0], s->macaddr[0],
s->macaddr[1], s->macaddr[1],
s->macaddr[2], s->macaddr[3], s->macaddr[4], s->macaddr[5]); s->macaddr[2], s->macaddr[3], s->macaddr[4], s->macaddr[5]);
register_savevm("lance", leaddr, 1, lance_save, lance_load, s); register_savevm("lance", leaddr, 1, lance_save, lance_load, s);
qemu_register_reset(lance_reset, s); qemu_register_reset(lance_reset, s);