openpic: switch IRQQueue queue from inline to bitmap
This is in preparation for using VMSTATE_BITMAP in a followup vmstate migration patch. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Alexander Graf <agraf@suse.de>
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				@ -200,11 +200,13 @@ typedef enum IRQType {
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    IRQ_TYPE_FSLSPECIAL,    /* FSL timer/IPI interrupt, edge, no polarity */
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					    IRQ_TYPE_FSLSPECIAL,    /* FSL timer/IPI interrupt, edge, no polarity */
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} IRQType;
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					} IRQType;
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					/* Round up to the nearest 64 IRQs so that the queue length
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					 * won't change when moving between 32 and 64 bit hosts.
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					 */
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					#define IRQQUEUE_SIZE_BITS ((OPENPIC_MAX_IRQ + 63) & ~63)
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typedef struct IRQQueue {
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					typedef struct IRQQueue {
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    /* Round up to the nearest 64 IRQs so that the queue length
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					    unsigned long *queue;
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     * won't change when moving between 32 and 64 bit hosts.
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     */
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    unsigned long queue[BITS_TO_LONGS((OPENPIC_MAX_IRQ + 63) & ~63)];
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    int next;
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					    int next;
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    int priority;
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					    int priority;
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} IRQQueue;
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					} IRQQueue;
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@ -1291,7 +1293,7 @@ static void openpic_save_IRQ_queue(QEMUFile* f, IRQQueue *q)
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{
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					{
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    unsigned int i;
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					    unsigned int i;
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    for (i = 0; i < ARRAY_SIZE(q->queue); i++) {
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					    for (i = 0; i < BITS_TO_LONGS(IRQQUEUE_SIZE_BITS); i++) {
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        /* Always put the lower half of a 64-bit long first, in case we
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					        /* Always put the lower half of a 64-bit long first, in case we
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         * restore on a 32-bit host.  The least significant bits correspond
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					         * restore on a 32-bit host.  The least significant bits correspond
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         * to lower IRQ numbers in the bitmap.
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					         * to lower IRQ numbers in the bitmap.
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@ -1345,7 +1347,7 @@ static void openpic_load_IRQ_queue(QEMUFile* f, IRQQueue *q)
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{
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					{
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    unsigned int i;
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					    unsigned int i;
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    for (i = 0; i < ARRAY_SIZE(q->queue); i++) {
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					    for (i = 0; i < BITS_TO_LONGS(IRQQUEUE_SIZE_BITS); i++) {
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        unsigned long val;
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					        unsigned long val;
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        val = qemu_get_be32(f);
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					        val = qemu_get_be32(f);
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@ -1444,12 +1446,14 @@ static void openpic_reset(DeviceState *d)
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        write_IRQreg_idr(opp, i, opp->idr_reset);
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					        write_IRQreg_idr(opp, i, opp->idr_reset);
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    }
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					    }
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    /* Initialise IRQ destinations */
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					    /* Initialise IRQ destinations */
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    for (i = 0; i < MAX_CPU; i++) {
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					    for (i = 0; i < opp->nb_cpus; i++) {
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        opp->dst[i].ctpr      = 15;
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					        opp->dst[i].ctpr      = 15;
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        memset(&opp->dst[i].raised, 0, sizeof(IRQQueue));
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        opp->dst[i].raised.next = -1;
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					        opp->dst[i].raised.next = -1;
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        memset(&opp->dst[i].servicing, 0, sizeof(IRQQueue));
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					        opp->dst[i].raised.priority = 0;
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					        bitmap_clear(opp->dst[i].raised.queue, 0, IRQQUEUE_SIZE_BITS);
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        opp->dst[i].servicing.next = -1;
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					        opp->dst[i].servicing.next = -1;
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					        opp->dst[i].servicing.priority = 0;
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					        bitmap_clear(opp->dst[i].servicing.queue, 0, IRQQUEUE_SIZE_BITS);
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    }
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					    }
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    /* Initialise timers */
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					    /* Initialise timers */
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    for (i = 0; i < OPENPIC_MAX_TMR; i++) {
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					    for (i = 0; i < OPENPIC_MAX_TMR; i++) {
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@ -1629,6 +1633,9 @@ static void openpic_realize(DeviceState *dev, Error **errp)
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        for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
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					        for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
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            sysbus_init_irq(d, &opp->dst[i].irqs[j]);
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					            sysbus_init_irq(d, &opp->dst[i].irqs[j]);
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        }
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					        }
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					        opp->dst[i].raised.queue = bitmap_new(IRQQUEUE_SIZE_BITS);
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					        opp->dst[i].servicing.queue = bitmap_new(IRQQUEUE_SIZE_BITS);
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    }
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					    }
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    register_savevm(dev, "openpic", 0, 2,
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					    register_savevm(dev, "openpic", 0, 2,
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