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target-arm: Move FPSID config to cpu init fns

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Move the reset FPSID to the ARMCPU struct, and set it in the
per-implementation instance init function. At reset we then
just copy the reset value into the CPUARMState field.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Peter Maydell 2012-04-20 17:58:32 +00:00
parent 581be09434
commit 325b3ceff6
3 changed files with 12 additions and 8 deletions
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1
target-arm/cpu-qom.h
View File

@ -70,6 +70,7 @@ typedef struct ARMCPU {
* prefix means a constant register. * prefix means a constant register.
*/ */
uint32_t midr; uint32_t midr;
uint32_t reset_fpsid;
} ARMCPU; } ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)

9
target-arm/cpu.c
View File

@ -100,6 +100,7 @@ static void arm926_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V5); set_feature(&cpu->env, ARM_FEATURE_V5);
set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM926; cpu->midr = ARM_CPUID_ARM926;
cpu->reset_fpsid = 0x41011090;
} }
static void arm946_initfn(Object *obj) static void arm946_initfn(Object *obj)
@ -117,6 +118,7 @@ static void arm1026_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_AUXCR); set_feature(&cpu->env, ARM_FEATURE_AUXCR);
cpu->midr = ARM_CPUID_ARM1026; cpu->midr = ARM_CPUID_ARM1026;
cpu->reset_fpsid = 0x410110a0;
} }
static void arm1136_r2_initfn(Object *obj) static void arm1136_r2_initfn(Object *obj)
@ -125,6 +127,7 @@ static void arm1136_r2_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V6); set_feature(&cpu->env, ARM_FEATURE_V6);
set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM1136_R2; cpu->midr = ARM_CPUID_ARM1136_R2;
cpu->reset_fpsid = 0x410120b4;
} }
static void arm1136_initfn(Object *obj) static void arm1136_initfn(Object *obj)
@ -134,6 +137,7 @@ static void arm1136_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V6); set_feature(&cpu->env, ARM_FEATURE_V6);
set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_VFP);
cpu->midr = ARM_CPUID_ARM1136; cpu->midr = ARM_CPUID_ARM1136;
cpu->reset_fpsid = 0x410120b4;
} }
static void arm1176_initfn(Object *obj) static void arm1176_initfn(Object *obj)
@ -143,6 +147,7 @@ static void arm1176_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_VAPA); set_feature(&cpu->env, ARM_FEATURE_VAPA);
cpu->midr = ARM_CPUID_ARM1176; cpu->midr = ARM_CPUID_ARM1176;
cpu->reset_fpsid = 0x410120b5;
} }
static void arm11mpcore_initfn(Object *obj) static void arm11mpcore_initfn(Object *obj)
@ -152,6 +157,7 @@ static void arm11mpcore_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_VAPA); set_feature(&cpu->env, ARM_FEATURE_VAPA);
cpu->midr = ARM_CPUID_ARM11MPCORE; cpu->midr = ARM_CPUID_ARM11MPCORE;
cpu->reset_fpsid = 0x410120b4;
} }
static void cortex_m3_initfn(Object *obj) static void cortex_m3_initfn(Object *obj)
@ -170,6 +176,7 @@ static void cortex_a8_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
cpu->midr = ARM_CPUID_CORTEXA8; cpu->midr = ARM_CPUID_CORTEXA8;
cpu->reset_fpsid = 0x410330c0;
} }
static void cortex_a9_initfn(Object *obj) static void cortex_a9_initfn(Object *obj)
@ -186,6 +193,7 @@ static void cortex_a9_initfn(Object *obj)
*/ */
set_feature(&cpu->env, ARM_FEATURE_V7MP); set_feature(&cpu->env, ARM_FEATURE_V7MP);
cpu->midr = ARM_CPUID_CORTEXA9; cpu->midr = ARM_CPUID_CORTEXA9;
cpu->reset_fpsid = 0x41033090;
} }
static void cortex_a15_initfn(Object *obj) static void cortex_a15_initfn(Object *obj)
@ -200,6 +208,7 @@ static void cortex_a15_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V7MP); set_feature(&cpu->env, ARM_FEATURE_V7MP);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
cpu->midr = ARM_CPUID_CORTEXA15; cpu->midr = ARM_CPUID_CORTEXA15;
cpu->reset_fpsid = 0x410430f0;
} }
static void ti925t_initfn(Object *obj) static void ti925t_initfn(Object *obj)

10
target-arm/helper.c
View File

@ -50,7 +50,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{ {
switch (id) { switch (id) {
case ARM_CPUID_ARM926: case ARM_CPUID_ARM926:
env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078; env->cp15.c1_sys = 0x00090078;
break; break;
@ -59,7 +58,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00000078; env->cp15.c1_sys = 0x00000078;
break; break;
case ARM_CPUID_ARM1026: case ARM_CPUID_ARM1026:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078; env->cp15.c1_sys = 0x00090078;
break; break;
@ -74,7 +72,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
* for 1136_r2 (in particular r0p2 does not actually implement most * for 1136_r2 (in particular r0p2 does not actually implement most
* of the ID registers). * of the ID registers).
*/ */
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
@ -83,7 +80,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00050078; env->cp15.c1_sys = 0x00050078;
break; break;
case ARM_CPUID_ARM1176: case ARM_CPUID_ARM1176:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t));
@ -92,7 +88,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00050078; env->cp15.c1_sys = 0x00050078;
break; break;
case ARM_CPUID_ARM11MPCORE: case ARM_CPUID_ARM11MPCORE:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
@ -100,7 +95,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_cachetype = 0x1dd20d2; env->cp15.c0_cachetype = 0x1dd20d2;
break; break;
case ARM_CPUID_CORTEXA8: case ARM_CPUID_CORTEXA8:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100; env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
@ -113,7 +107,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078; env->cp15.c1_sys = 0x00c50078;
break; break;
case ARM_CPUID_CORTEXA9: case ARM_CPUID_CORTEXA9:
env->vfp.xregs[ARM_VFP_FPSID] = 0x41033090;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222; env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111; env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
@ -125,7 +118,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00c50078; env->cp15.c1_sys = 0x00c50078;
break; break;
case ARM_CPUID_CORTEXA15: case ARM_CPUID_CORTEXA15:
env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222; env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111; env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t)); memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t));
@ -201,6 +193,8 @@ void cpu_state_reset(CPUARMState *env)
cpu_reset_model_id(env, id); cpu_reset_model_id(env, id);
env->cp15.c15_config_base_address = tmp; env->cp15.c15_config_base_address = tmp;
env->cp15.c0_cpuid = cpu->midr; env->cp15.c0_cpuid = cpu->midr;
env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
#if defined (CONFIG_USER_ONLY) #if defined (CONFIG_USER_ONLY)
env->uncached_cpsr = ARM_CPU_MODE_USR; env->uncached_cpsr = ARM_CPU_MODE_USR;
/* For user mode we must enable access to coprocessors */ /* For user mode we must enable access to coprocessors */