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tcg-s390: Implement mulu2_i64 opcode

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Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2013-03-26 16:50:29 -04:00
parent 3790b9180a
commit 36017dc68a
2 changed files with 6 additions and 1 deletions
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5
tcg/s390/tcg-target.c
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@ -147,6 +147,7 @@ typedef enum S390Opcode {
RRE_LRVR = 0xb91f, RRE_LRVR = 0xb91f,
RRE_LRVGR = 0xb90f, RRE_LRVGR = 0xb90f,
RRE_LTGR = 0xb902, RRE_LTGR = 0xb902,
RRE_MLGR = 0xb986,
RRE_MSGR = 0xb90c, RRE_MSGR = 0xb90c,
RRE_MSR = 0xb252, RRE_MSR = 0xb252,
RRE_NGR = 0xb980, RRE_NGR = 0xb980,
@ -1981,6 +1982,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_divu2_i64: case INDEX_op_divu2_i64:
tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, args[4]); tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, args[4]);
break; break;
case INDEX_op_mulu2_i64:
tcg_out_insn(s, RRE, MLGR, TCG_REG_R2, args[3]);
break;
case INDEX_op_shl_i64: case INDEX_op_shl_i64:
op = RSY_SLLG; op = RSY_SLLG;
@ -2156,6 +2160,7 @@ static const TCGTargetOpDef s390_op_defs[] = {
{ INDEX_op_div2_i64, { "b", "a", "0", "1", "r" } }, { INDEX_op_div2_i64, { "b", "a", "0", "1", "r" } },
{ INDEX_op_divu2_i64, { "b", "a", "0", "1", "r" } }, { INDEX_op_divu2_i64, { "b", "a", "0", "1", "r" } },
{ INDEX_op_mulu2_i64, { "b", "a", "0", "r" } },
{ INDEX_op_and_i64, { "r", "0", "rA" } }, { INDEX_op_and_i64, { "r", "0", "rA" } },
{ INDEX_op_or_i64, { "r", "0", "rO" } }, { INDEX_op_or_i64, { "r", "0", "rO" } },

2
tcg/s390/tcg-target.h
View File

@ -92,7 +92,7 @@ typedef enum TCGReg {
#define TCG_TARGET_HAS_movcond_i64 0 #define TCG_TARGET_HAS_movcond_i64 0
#define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 0 #define TCG_TARGET_HAS_mulu2_i64 1
#define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_muls2_i64 0
/* used for function call generation */ /* used for function call generation */