hw/unicore32: restrict hw addr defines to source file
and drop unused #includes Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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				| @ -11,16 +11,11 @@ | ||||
| 
 | ||||
| #include "qemu/osdep.h" | ||||
| #include "qapi/error.h" | ||||
| #include "qemu-common.h" | ||||
| #include "cpu.h" | ||||
| #include "ui/console.h" | ||||
| #include "elf.h" | ||||
| #include "exec/address-spaces.h" | ||||
| #include "hw/sysbus.h" | ||||
| #include "hw/boards.h" | ||||
| #include "hw/loader.h" | ||||
| #include "hw/i386/pc.h" | ||||
| #include "qemu/error-report.h" | ||||
| #include "sysemu/qtest.h" | ||||
| 
 | ||||
| #undef DEBUG_PUV3 | ||||
| @ -29,6 +24,16 @@ | ||||
| #define KERNEL_LOAD_ADDR        0x03000000 | ||||
| #define KERNEL_MAX_SIZE         0x00800000 /* Just a guess */ | ||||
| 
 | ||||
| /* PKUnity System bus (AHB): 0xc0000000 - 0xedffffff (640MB) */ | ||||
| #define PUV3_DMA_BASE           (0xc0200000) /* AHB-4 */ | ||||
| 
 | ||||
| /* PKUnity Peripheral bus (APB): 0xee000000 - 0xefffffff (128MB) */ | ||||
| #define PUV3_GPIO_BASE          (0xee500000) /* APB-5 */ | ||||
| #define PUV3_INTC_BASE          (0xee600000) /* APB-6 */ | ||||
| #define PUV3_OST_BASE           (0xee800000) /* APB-8 */ | ||||
| #define PUV3_PM_BASE            (0xeea00000) /* APB-10 */ | ||||
| #define PUV3_PS2_BASE           (0xeeb00000) /* APB-11 */ | ||||
| 
 | ||||
| static void puv3_intc_cpu_handler(void *opaque, int irq, int level) | ||||
| { | ||||
|     UniCore32CPU *cpu = opaque; | ||||
|  | ||||
| @ -14,16 +14,6 @@ | ||||
| 
 | ||||
| #define PUV3_REGS_OFFSET        (0x1000) /* 4K is reasonable */ | ||||
| 
 | ||||
| /* PKUnity System bus (AHB): 0xc0000000 - 0xedffffff (640MB) */ | ||||
| #define PUV3_DMA_BASE           (0xc0200000) /* AHB-4 */ | ||||
| 
 | ||||
| /* PKUnity Peripheral bus (APB): 0xee000000 - 0xefffffff (128MB) */ | ||||
| #define PUV3_GPIO_BASE          (0xee500000) /* APB-5 */ | ||||
| #define PUV3_INTC_BASE          (0xee600000) /* APB-6 */ | ||||
| #define PUV3_OST_BASE           (0xee800000) /* APB-8 */ | ||||
| #define PUV3_PM_BASE            (0xeea00000) /* APB-10 */ | ||||
| #define PUV3_PS2_BASE           (0xeeb00000) /* APB-11 */ | ||||
| 
 | ||||
| /* Hardware interrupts */ | ||||
| #define PUV3_IRQS_NR            (32) | ||||
| 
 | ||||
|  | ||||
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