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intc/arm_gic: Remove some dead code and put some functions static

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Some functions are now only used in arm_gic.c, put them static. Some of
them where only used by the NVIC implementation and are not used
anymore, so remove them.

Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180727095421.386-4-luc.michel@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Luc Michel 2018-08-14 17:17:20 +01:00 committed by Peter Maydell
parent 3bb0b03897
commit 50491c56a5
2 changed files with 2 additions and 25 deletions
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23
hw/intc/arm_gic.c
View File

@ -71,7 +71,7 @@ static inline bool gic_has_groups(GICState *s)
/* TODO: Many places that call this routine could be optimized. */ /* TODO: Many places that call this routine could be optimized. */
/* Update interrupt status after enabled or pending bits have been changed. */ /* Update interrupt status after enabled or pending bits have been changed. */
void gic_update(GICState *s) static void gic_update(GICState *s)
{ {
int best_irq; int best_irq;
int best_prio; int best_prio;
@ -137,19 +137,6 @@ void gic_update(GICState *s)
} }
} }
void gic_set_pending_private(GICState *s, int cpu, int irq)
{
int cm = 1 << cpu;
if (gic_test_pending(s, irq, cm)) {
return;
}
DPRINTF("Set %d pending cpu %d\n", irq, cpu);
GIC_DIST_SET_PENDING(irq, cm);
gic_update(s);
}
static void gic_set_irq_11mpcore(GICState *s, int irq, int level, static void gic_set_irq_11mpcore(GICState *s, int irq, int level,
int cm, int target) int cm, int target)
{ {
@ -579,7 +566,7 @@ static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
GIC_DIST_CLEAR_ACTIVE(irq, cm); GIC_DIST_CLEAR_ACTIVE(irq, cm);
} }
void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
{ {
int cm = 1 << cpu; int cm = 1 << cpu;
int group; int group;
@ -1488,12 +1475,6 @@ static const MemoryRegionOps gic_cpu_ops = {
.endianness = DEVICE_NATIVE_ENDIAN, .endianness = DEVICE_NATIVE_ENDIAN,
}; };
/* This function is used by nvic model */
void gic_init_irqs_and_distributor(GICState *s)
{
gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops);
}
static void arm_gic_realize(DeviceState *dev, Error **errp) static void arm_gic_realize(DeviceState *dev, Error **errp)
{ {
/* Device instance realize function for the GIC sysbus device */ /* Device instance realize function for the GIC sysbus device */

4
hw/intc/gic_internal.h
View File

@ -75,11 +75,7 @@
/* The special cases for the revision property: */ /* The special cases for the revision property: */
#define REV_11MPCORE 0 #define REV_11MPCORE 0
void gic_set_pending_private(GICState *s, int cpu, int irq);
uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs); uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs);
void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs);
void gic_update(GICState *s);
void gic_init_irqs_and_distributor(GICState *s);
void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val,
MemTxAttrs attrs); MemTxAttrs attrs);