Write zeros to high bits of y, based on patch by Vince Weaver
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5196 c046a42c-6fe2-441c-8c8c-71466251a162
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				@ -709,7 +709,8 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
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    tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
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					    tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
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    tcg_gen_shli_tl(r_temp, r_temp, 31);
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					    tcg_gen_shli_tl(r_temp, r_temp, 31);
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    tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1);
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					    tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1);
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    tcg_gen_or_tl(cpu_y, cpu_tmp0, r_temp);
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					    tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp);
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					    tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
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    // b1 = N ^ V;
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					    // b1 = N ^ V;
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    gen_mov_reg_N(cpu_tmp0, cpu_psr);
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					    gen_mov_reg_N(cpu_tmp0, cpu_psr);
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@ -3195,7 +3196,8 @@ static void disas_sparc_insn(DisasContext * dc)
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                        {
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					                        {
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                            switch(rd) {
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					                            switch(rd) {
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                            case 0: /* wry */
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					                            case 0: /* wry */
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                                tcg_gen_xor_tl(cpu_y, cpu_src1, cpu_src2);
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					                                tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
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					                                tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
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                                break;
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					                                break;
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#ifndef TARGET_SPARC64
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					#ifndef TARGET_SPARC64
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                            case 0x01 ... 0x0f: /* undefined in the
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					                            case 0x01 ... 0x0f: /* undefined in the
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