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target-mips: copy CP0_Config1 into DisasContext

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In order to avoid access to the CPUMIPSState structure in the
translator, keep a copy of CP0_Config1 into DisasContext. The whole
register is read-only so it can be copied as a single value.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2014-05-29 15:50:17 +02:00
parent d70a319b8d
commit 5ab5c04170
1 changed files with 11 additions and 9 deletions
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20
target-mips/translate.c
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@ -1067,6 +1067,7 @@ typedef struct DisasContext {
uint32_t opcode; uint32_t opcode;
int singlestep_enabled; int singlestep_enabled;
int insn_flags; int insn_flags;
int32_t CP0_Config1;
/* Routine used to access memory */ /* Routine used to access memory */
int mem_idx; int mem_idx;
uint32_t hflags, saved_hflags; uint32_t hflags, saved_hflags;
@ -1921,10 +1922,10 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
tcg_temp_free(t0); tcg_temp_free(t0);
} }
static void gen_cop1_ldst(CPUMIPSState *env, DisasContext *ctx, static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt,
uint32_t op, int rt, int rs, int16_t imm) int rs, int16_t imm)
{ {
if (env->CP0_Config1 & (1 << CP0C1_FP)) { if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx); check_cp1_enabled(ctx);
gen_flt_ldst(ctx, op, rt, rs, imm); gen_flt_ldst(ctx, op, rt, rs, imm);
} else { } else {
@ -11838,7 +11839,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx,
} }
break; break;
case POOL32F: case POOL32F:
if (env->CP0_Config1 & (1 << CP0C1_FP)) { if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
minor = ctx->opcode & 0x3f; minor = ctx->opcode & 0x3f;
check_cp1_enabled(ctx); check_cp1_enabled(ctx);
switch (minor) { switch (minor) {
@ -12352,7 +12353,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx,
case SDC132: case SDC132:
mips32_op = OPC_SDC1; mips32_op = OPC_SDC1;
do_cop1: do_cop1:
gen_cop1_ldst(env, ctx, mips32_op, rt, rs, imm); gen_cop1_ldst(ctx, mips32_op, rt, rs, imm);
break; break;
case ADDIUPC: case ADDIUPC:
{ {
@ -14600,7 +14601,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
case OPC_MOVCI: case OPC_MOVCI:
check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
if (env->CP0_Config1 & (1 << CP0C1_FP)) { if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx); check_cp1_enabled(ctx);
gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7, gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
(ctx->opcode >> 16) & 1); (ctx->opcode >> 16) & 1);
@ -15479,11 +15480,11 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
case OPC_LDC1: case OPC_LDC1:
case OPC_SWC1: case OPC_SWC1:
case OPC_SDC1: case OPC_SDC1:
gen_cop1_ldst(env, ctx, op, rt, rs, imm); gen_cop1_ldst(ctx, op, rt, rs, imm);
break; break;
case OPC_CP1: case OPC_CP1:
if (env->CP0_Config1 & (1 << CP0C1_FP)) { if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx); check_cp1_enabled(ctx);
op1 = MASK_CP1(ctx->opcode); op1 = MASK_CP1(ctx->opcode);
switch (op1) { switch (op1) {
@ -15545,7 +15546,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
break; break;
case OPC_CP3: case OPC_CP3:
if (env->CP0_Config1 & (1 << CP0C1_FP)) { if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx); check_cp1_enabled(ctx);
op1 = MASK_CP3(ctx->opcode); op1 = MASK_CP3(ctx->opcode);
switch (op1) { switch (op1) {
@ -15653,6 +15654,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
ctx.saved_pc = -1; ctx.saved_pc = -1;
ctx.singlestep_enabled = cs->singlestep_enabled; ctx.singlestep_enabled = cs->singlestep_enabled;
ctx.insn_flags = env->insn_flags; ctx.insn_flags = env->insn_flags;
ctx.CP0_Config1 = env->CP0_Config1;
ctx.tb = tb; ctx.tb = tb;
ctx.bstate = BS_NONE; ctx.bstate = BS_NONE;
/* Restore delay slot state from the tb context. */ /* Restore delay slot state from the tb context. */