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Remove Sun4c, Sun4d and a few CPUs

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Sun4c and Sun4d architectures and related CPUs are not fully implemented
(especially Sun4c MMU) and there has been no interest for them.

Likewise, a few CPUs (Cypress, Ross etc) are only half implemented.

Remove the machines and CPUs, they can be re-added if needed later.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl 2013-04-14 18:10:28 +00:00
parent 4f6ab397b6
commit 6a4e177114
6 changed files with 6 additions and 955 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/intc/Makefile.objs
View File

@ -7,7 +7,7 @@ common-obj-$(CONFIG_ETRAXFS) += etraxfs_pic.o
common-obj-$(CONFIG_IMX) += imx_avic.o
common-obj-$(CONFIG_LM32) += lm32_pic.o
common-obj-$(CONFIG_REALVIEW) += realview_gic.o
common-obj-$(CONFIG_SLAVIO) += sbi.o slavio_intctl.o sun4c_intctl.o
common-obj-$(CONFIG_SLAVIO) += slavio_intctl.o
common-obj-$(CONFIG_IOAPIC) += ioapic_common.o
common-obj-$(CONFIG_ARM_GIC) += arm_gic_common.o

156
hw/intc/sbi.c
View File

@ -1,156 +0,0 @@
/*
* QEMU Sparc SBI interrupt controller emulation
*
* Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "hw/sysbus.h"
//#define DEBUG_IRQ
#ifdef DEBUG_IRQ
#define DPRINTF(fmt, ...) \
do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...)
#endif
#define MAX_CPUS 16
#define SBI_NREGS 16
typedef struct SBIState {
SysBusDevice busdev;
MemoryRegion iomem;
uint32_t regs[SBI_NREGS];
uint32_t intreg_pending[MAX_CPUS];
qemu_irq cpu_irqs[MAX_CPUS];
uint32_t pil_out[MAX_CPUS];
} SBIState;
#define SBI_SIZE (SBI_NREGS * 4)
static void sbi_set_irq(void *opaque, int irq, int level)
{
}
static uint64_t sbi_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
SBIState *s = opaque;
uint32_t saddr, ret;
saddr = addr >> 2;
switch (saddr) {
default:
ret = s->regs[saddr];
break;
}
DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
return ret;
}
static void sbi_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned dize)
{
SBIState *s = opaque;
uint32_t saddr;
saddr = addr >> 2;
DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, (int)val);
switch (saddr) {
default:
s->regs[saddr] = val;
break;
}
}
static const MemoryRegionOps sbi_mem_ops = {
.read = sbi_mem_read,
.write = sbi_mem_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static const VMStateDescription vmstate_sbi = {
.name ="sbi",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField []) {
VMSTATE_UINT32_ARRAY(intreg_pending, SBIState, MAX_CPUS),
VMSTATE_END_OF_LIST()
}
};
static void sbi_reset(DeviceState *d)
{
SBIState *s = container_of(d, SBIState, busdev.qdev);
unsigned int i;
for (i = 0; i < MAX_CPUS; i++) {
s->intreg_pending[i] = 0;
}
}
static int sbi_init1(SysBusDevice *dev)
{
SBIState *s = FROM_SYSBUS(SBIState, dev);
unsigned int i;
qdev_init_gpio_in(&dev->qdev, sbi_set_irq, 32 + MAX_CPUS);
for (i = 0; i < MAX_CPUS; i++) {
sysbus_init_irq(dev, &s->cpu_irqs[i]);
}
memory_region_init_io(&s->iomem, &sbi_mem_ops, s, "sbi", SBI_SIZE);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
static void sbi_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = sbi_init1;
dc->reset = sbi_reset;
dc->vmsd = &vmstate_sbi;
}
static const TypeInfo sbi_info = {
.name = "sbi",
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SBIState),
.class_init = sbi_class_init,
};
static void sbi_register_types(void)
{
type_register_static(&sbi_info);
}
type_init(sbi_register_types)

208
hw/intc/sun4c_intctl.c
View File

@ -1,208 +0,0 @@
/*
* QEMU Sparc Sun4c interrupt controller emulation
*
* Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "hw/hw.h"
#include "hw/sparc/sun4m.h"
#include "monitor/monitor.h"
#include "hw/sysbus.h"
//#define DEBUG_IRQ_COUNT
//#define DEBUG_IRQ
#ifdef DEBUG_IRQ
#define DPRINTF(fmt, ...) \
do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...)
#endif
/*
* Registers of interrupt controller in sun4c.
*
*/
#define MAX_PILS 16
typedef struct Sun4c_INTCTLState {
SysBusDevice busdev;
MemoryRegion iomem;
#ifdef DEBUG_IRQ_COUNT
uint64_t irq_count;
#endif
qemu_irq cpu_irqs[MAX_PILS];
const uint32_t *intbit_to_level;
uint32_t pil_out;
uint8_t reg;
uint8_t pending;
} Sun4c_INTCTLState;
#define INTCTL_SIZE 1
static void sun4c_check_interrupts(void *opaque);
static uint64_t sun4c_intctl_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
Sun4c_INTCTLState *s = opaque;
uint32_t ret;
ret = s->reg;
DPRINTF("read reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
return ret;
}
static void sun4c_intctl_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
Sun4c_INTCTLState *s = opaque;
DPRINTF("write reg 0x" TARGET_FMT_plx " = %x\n", addr, (unsigned)val);
val &= 0xbf;
s->reg = val;
sun4c_check_interrupts(s);
}
static const MemoryRegionOps sun4c_intctl_mem_ops = {
.read = sun4c_intctl_mem_read,
.write = sun4c_intctl_mem_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 1,
.max_access_size = 1,
},
};
static const uint32_t intbit_to_level[] = { 0, 1, 4, 6, 8, 10, 0, 14, };
static void sun4c_check_interrupts(void *opaque)
{
Sun4c_INTCTLState *s = opaque;
uint32_t pil_pending;
unsigned int i;
pil_pending = 0;
if (s->pending && !(s->reg & 0x80000000)) {
for (i = 0; i < 8; i++) {
if (s->pending & (1 << i))
pil_pending |= 1 << intbit_to_level[i];
}
}
for (i = 0; i < MAX_PILS; i++) {
if (pil_pending & (1 << i)) {
if (!(s->pil_out & (1 << i)))
qemu_irq_raise(s->cpu_irqs[i]);
} else {
if (s->pil_out & (1 << i))
qemu_irq_lower(s->cpu_irqs[i]);
}
}
s->pil_out = pil_pending;
}
/*
* "irq" here is the bit number in the system interrupt register
*/
static void sun4c_set_irq(void *opaque, int irq, int level)
{
Sun4c_INTCTLState *s = opaque;
uint32_t mask = 1 << irq;
uint32_t pil = intbit_to_level[irq];
DPRINTF("Set irq %d -> pil %d level %d\n", irq, pil,
level);
if (pil > 0) {
if (level) {
#ifdef DEBUG_IRQ_COUNT
s->irq_count++;
#endif
s->pending |= mask;
} else {
s->pending &= ~mask;
}
sun4c_check_interrupts(s);
}
}
static const VMStateDescription vmstate_sun4c_intctl = {
.name ="sun4c_intctl",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField []) {
VMSTATE_UINT8(reg, Sun4c_INTCTLState),
VMSTATE_UINT8(pending, Sun4c_INTCTLState),
VMSTATE_END_OF_LIST()
}
};
static void sun4c_intctl_reset(DeviceState *d)
{
Sun4c_INTCTLState *s = container_of(d, Sun4c_INTCTLState, busdev.qdev);
s->reg = 1;
s->pending = 0;
}
static int sun4c_intctl_init1(SysBusDevice *dev)
{
Sun4c_INTCTLState *s = FROM_SYSBUS(Sun4c_INTCTLState, dev);
unsigned int i;
memory_region_init_io(&s->iomem, &sun4c_intctl_mem_ops, s,
"intctl", INTCTL_SIZE);
sysbus_init_mmio(dev, &s->iomem);
qdev_init_gpio_in(&dev->qdev, sun4c_set_irq, 8);
for (i = 0; i < MAX_PILS; i++) {
sysbus_init_irq(dev, &s->cpu_irqs[i]);
}
return 0;
}
static void sun4c_intctl_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = sun4c_intctl_init1;
dc->reset = sun4c_intctl_reset;
dc->vmsd = &vmstate_sun4c_intctl;
}
static const TypeInfo sun4c_intctl_info = {
.name = "sun4c_intctl",
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Sun4c_INTCTLState),
.class_init = sun4c_intctl_class_init,
};
static void sun4c_intctl_register_types(void)
{
type_register_static(&sun4c_intctl_info);
}
type_init(sun4c_intctl_register_types)

463
hw/sparc/sun4m.c
View File

@ -55,18 +55,6 @@
* SPARCstation 20/xx, SPARCserver 20
* SPARCstation 4
*
* Sun4d architecture was used in the following machines:
*
* SPARCcenter 2000
* SPARCserver 1000
*
* Sun4c architecture was used in the following machines:
* SPARCstation 1/1+, SPARCserver 1/1+
* SPARCstation SLC
* SPARCstation IPC
* SPARCstation ELC
* SPARCstation IPX
*
* See for example: http://www.sunhelp.org/faq/sunref1.html
*/
@ -104,36 +92,6 @@ struct sun4m_hwdef {
uint8_t nvram_machine_id;
};
#define MAX_IOUNITS 5
struct sun4d_hwdef {
hwaddr iounit_bases[MAX_IOUNITS], slavio_base;
hwaddr counter_base, nvram_base, ms_kb_base;
hwaddr serial_base;
hwaddr espdma_base, esp_base;
hwaddr ledma_base, le_base;
hwaddr tcx_base;
hwaddr sbi_base;
uint64_t max_mem;
const char * const default_cpu_model;
uint32_t iounit_version;
uint16_t machine_id;
uint8_t nvram_machine_id;
};
struct sun4c_hwdef {
hwaddr iommu_base, slavio_base;
hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
hwaddr serial_base, fd_base;
hwaddr idreg_base, dma_base, esp_base, le_base;
hwaddr tcx_base, aux1_base;
uint64_t max_mem;
const char * const default_cpu_model;
uint32_t iommu_version;
uint16_t machine_id;
uint8_t nvram_machine_id;
};
int DMA_get_channel_mode (int nchan)
{
return 0;
@ -1052,7 +1010,6 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
}
enum {
ss2_id = 0,
ss5_id = 32,
vger_id,
lx_id,
@ -1062,8 +1019,6 @@ enum {
ss10_id = 64,
ss20_id,
ss600mp_id,
ss1000_id = 96,
ss2000_id,
};
static const struct sun4m_hwdef sun4m_hwdefs[] = {
@ -1504,417 +1459,6 @@ static QEMUMachine sbook_machine = {
DEFAULT_MACHINE_OPTIONS,
};
static const struct sun4d_hwdef sun4d_hwdefs[] = {
/* SS-1000 */
{
.iounit_bases = {
0xfe0200000ULL,
0xfe1200000ULL,
0xfe2200000ULL,
0xfe3200000ULL,
-1,
},
.tcx_base = 0x820000000ULL,
.slavio_base = 0xf00000000ULL,
.ms_kb_base = 0xf00240000ULL,
.serial_base = 0xf00200000ULL,
.nvram_base = 0xf00280000ULL,
.counter_base = 0xf00300000ULL,
.espdma_base = 0x800081000ULL,
.esp_base = 0x800080000ULL,
.ledma_base = 0x800040000ULL,
.le_base = 0x800060000ULL,
.sbi_base = 0xf02800000ULL,
.nvram_machine_id = 0x80,
.machine_id = ss1000_id,
.iounit_version = 0x03000000,
.max_mem = 0xf00000000ULL,
.default_cpu_model = "TI SuperSparc II",
},
/* SS-2000 */
{
.iounit_bases = {
0xfe0200000ULL,
0xfe1200000ULL,
0xfe2200000ULL,
0xfe3200000ULL,
0xfe4200000ULL,
},
.tcx_base = 0x820000000ULL,
.slavio_base = 0xf00000000ULL,
.ms_kb_base = 0xf00240000ULL,
.serial_base = 0xf00200000ULL,
.nvram_base = 0xf00280000ULL,
.counter_base = 0xf00300000ULL,
.espdma_base = 0x800081000ULL,
.esp_base = 0x800080000ULL,
.ledma_base = 0x800040000ULL,
.le_base = 0x800060000ULL,
.sbi_base = 0xf02800000ULL,
.nvram_machine_id = 0x80,
.machine_id = ss2000_id,
.iounit_version = 0x03000000,
.max_mem = 0xf00000000ULL,
.default_cpu_model = "TI SuperSparc II",
},
};
static DeviceState *sbi_init(hwaddr addr, qemu_irq **parent_irq)
{
DeviceState *dev;
SysBusDevice *s;
unsigned int i;
dev = qdev_create(NULL, "sbi");
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
for (i = 0; i < MAX_CPUS; i++) {
sysbus_connect_irq(s, i, *parent_irq[i]);
}
sysbus_mmio_map(s, 0, addr);
return dev;
}
static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
unsigned int i;
void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
espdma_irq, ledma_irq;
qemu_irq esp_reset, dma_enable;
unsigned long kernel_size;
void *fw_cfg;
DeviceState *dev;
/* init CPUs */
if (!cpu_model)
cpu_model = hwdef->default_cpu_model;
for(i = 0; i < smp_cpus; i++) {
cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
}
for (i = smp_cpus; i < MAX_CPUS; i++)
cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
/* set up devices */
ram_init(0, RAM_size, hwdef->max_mem);
prom_init(hwdef->slavio_base, bios_name);
dev = sbi_init(hwdef->sbi_base, cpu_irqs);
for (i = 0; i < 32; i++) {
sbi_irq[i] = qdev_get_gpio_in(dev, i);
}
for (i = 0; i < MAX_CPUS; i++) {
sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
}
for (i = 0; i < MAX_IOUNITS; i++)
if (hwdef->iounit_bases[i] != (hwaddr)-1)
iounits[i] = iommu_init(hwdef->iounit_bases[i],
hwdef->iounit_version,
sbi_irq[0]);
espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
iounits[0], &espdma_irq, 0);
/* should be lebuffer instead */
ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
iounits[0], &ledma_irq, 0);
if (graphic_depth != 8 && graphic_depth != 24) {
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
exit (1);
}
tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
graphic_depth);
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
/* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
if (drive_get_max_bus(IF_SCSI) > 0) {
fprintf(stderr, "qemu: too many SCSI bus\n");
exit(1);
}
esp_init(hwdef->esp_base, 2,
espdma_memory_read, espdma_memory_write,
espdma, espdma_irq, &esp_reset, &dma_enable);
qdev_connect_gpio_out(espdma, 0, esp_reset);
qdev_connect_gpio_out(espdma, 1, dma_enable);
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
RAM_size);
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
boot_device, RAM_size, kernel_size, graphic_width,
graphic_height, graphic_depth, hwdef->nvram_machine_id,
"Sun4d");
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
}
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
/* SPARCserver 1000 hardware initialisation */
static void ss1000_init(QEMUMachineInitArgs *args)
{
ram_addr_t RAM_size = args->ram_size;
const char *cpu_model = args->cpu_model;
const char *kernel_filename = args->kernel_filename;
const char *kernel_cmdline = args->kernel_cmdline;
const char *initrd_filename = args->initrd_filename;
const char *boot_device = args->boot_device;
sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
/* SPARCcenter 2000 hardware initialisation */
static void ss2000_init(QEMUMachineInitArgs *args)
{
ram_addr_t RAM_size = args->ram_size;
const char *cpu_model = args->cpu_model;
const char *kernel_filename = args->kernel_filename;
const char *kernel_cmdline = args->kernel_cmdline;
const char *initrd_filename = args->initrd_filename;
const char *boot_device = args->boot_device;
sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
static QEMUMachine ss1000_machine = {
.name = "SS-1000",
.desc = "Sun4d platform, SPARCserver 1000",
.init = ss1000_init,
.block_default_type = IF_SCSI,
.max_cpus = 8,
DEFAULT_MACHINE_OPTIONS,
};
static QEMUMachine ss2000_machine = {
.name = "SS-2000",
.desc = "Sun4d platform, SPARCcenter 2000",
.init = ss2000_init,
.block_default_type = IF_SCSI,
.max_cpus = 20,
DEFAULT_MACHINE_OPTIONS,
};
static const struct sun4c_hwdef sun4c_hwdefs[] = {
/* SS-2 */
{
.iommu_base = 0xf8000000,
.tcx_base = 0xfe000000,
.slavio_base = 0xf6000000,
.intctl_base = 0xf5000000,
.counter_base = 0xf3000000,
.ms_kb_base = 0xf0000000,
.serial_base = 0xf1000000,
.nvram_base = 0xf2000000,
.fd_base = 0xf7200000,
.dma_base = 0xf8400000,
.esp_base = 0xf8800000,
.le_base = 0xf8c00000,
.aux1_base = 0xf7400003,
.nvram_machine_id = 0x55,
.machine_id = ss2_id,
.max_mem = 0x10000000,
.default_cpu_model = "Cypress CY7C601",
},
};
static DeviceState *sun4c_intctl_init(hwaddr addr,
qemu_irq *parent_irq)
{
DeviceState *dev;
SysBusDevice *s;
unsigned int i;
dev = qdev_create(NULL, "sun4c_intctl");
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
for (i = 0; i < MAX_PILS; i++) {
sysbus_connect_irq(s, i, parent_irq[i]);
}
sysbus_mmio_map(s, 0, addr);
return dev;
}
static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
void *iommu, *espdma, *ledma, *nvram;
qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
qemu_irq esp_reset, dma_enable;
qemu_irq fdc_tc;
unsigned long kernel_size;
DriveInfo *fd[MAX_FD];
void *fw_cfg;
DeviceState *dev;
unsigned int i;
/* init CPU */
if (!cpu_model)
cpu_model = hwdef->default_cpu_model;
cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
/* set up devices */
ram_init(0, RAM_size, hwdef->max_mem);
prom_init(hwdef->slavio_base, bios_name);
dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
for (i = 0; i < 8; i++) {
slavio_irq[i] = qdev_get_gpio_in(dev, i);
}
iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
slavio_irq[1]);
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
iommu, &espdma_irq, 0);
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
slavio_irq[3], iommu, &ledma_irq, 1);
if (graphic_depth != 8 && graphic_depth != 24) {
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
exit (1);
}
tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
graphic_depth);
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
/* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
escc_init(hwdef->serial_base, slavio_irq[1],
slavio_irq[1], serial_hds[0], serial_hds[1],
ESCC_CLOCK, 1);
if (hwdef->fd_base != (hwaddr)-1) {
/* there is zero or one floppy drive */
memset(fd, 0, sizeof(fd));
fd[0] = drive_get(IF_FLOPPY, 0, 0);
sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
&fdc_tc);
} else {
fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
}
slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
if (drive_get_max_bus(IF_SCSI) > 0) {
fprintf(stderr, "qemu: too many SCSI bus\n");
exit(1);
}
esp_init(hwdef->esp_base, 2,
espdma_memory_read, espdma_memory_write,
espdma, espdma_irq, &esp_reset, &dma_enable);
qdev_connect_gpio_out(espdma, 0, esp_reset);
qdev_connect_gpio_out(espdma, 1, dma_enable);
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
RAM_size);
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
boot_device, RAM_size, kernel_size, graphic_width,
graphic_height, graphic_depth, hwdef->nvram_machine_id,
"Sun4c");
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
}
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
/* SPARCstation 2 hardware initialisation */
static void ss2_init(QEMUMachineInitArgs *args)
{
ram_addr_t RAM_size = args->ram_size;
const char *cpu_model = args->cpu_model;
const char *kernel_filename = args->kernel_filename;
const char *kernel_cmdline = args->kernel_cmdline;
const char *initrd_filename = args->initrd_filename;
const char *boot_device = args->boot_device;
sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
static QEMUMachine ss2_machine = {
.name = "SS-2",
.desc = "Sun4c platform, SPARCstation 2",
.init = ss2_init,
.block_default_type = IF_SCSI,
DEFAULT_MACHINE_OPTIONS,
};
static void sun4m_register_types(void)
{
type_register_static(&idreg_info);
@ -1923,7 +1467,7 @@ static void sun4m_register_types(void)
type_register_static(&ram_info);
}
static void ss2_machine_init(void)
static void sun4m_machine_init(void)
{
qemu_register_machine(&ss5_machine);
qemu_register_machine(&ss10_machine);
@ -1934,10 +1478,7 @@ static void ss2_machine_init(void)
qemu_register_machine(&ss4_machine);
qemu_register_machine(&scls_machine);
qemu_register_machine(&sbook_machine);
qemu_register_machine(&ss1000_machine);
qemu_register_machine(&ss2000_machine);
qemu_register_machine(&ss2_machine);
}
type_init(sun4m_register_types)
machine_init(ss2_machine_init);
machine_init(sun4m_machine_init);

10
qemu-doc.texi
View File

@ -1958,15 +1958,11 @@ SPARCbook
The emulation is somewhat complete. SMP up to 16 CPUs is supported,
but Linux limits the number of usable CPUs to 4.
It's also possible to simulate a SPARCstation 2 (sun4c architecture),
SPARCserver 1000, or SPARCcenter 2000 (sun4d architecture), but these
emulators are not usable yet.
QEMU emulates the following sun4m/sun4c/sun4d peripherals:
QEMU emulates the following sun4m peripherals:
@itemize @minus
@item
IOMMU or IO-UNITs
IOMMU
@item
TCX Frame buffer
@item
@ -2019,7 +2015,7 @@ qemu-system-sparc -prom-env 'auto-boot?=false' \
-prom-env 'boot-device=sd(0,2,0):d' -prom-env 'boot-args=linux single'
@end example
@item -M [SS-4|SS-5|SS-10|SS-20|SS-600MP|LX|Voyager|SPARCClassic] [|SPARCbook|SS-2|SS-1000|SS-2000]
@item -M [SS-4|SS-5|SS-10|SS-20|SS-600MP|LX|Voyager|SPARCClassic] [|SPARCbook]
Set the emulated machine type. Default is SS-5.

122
target-sparc/cpu.c
View File

@ -291,19 +291,6 @@ static const sparc_def_t sparc_defs[] = {
.features = CPU_DEFAULT_FEATURES,
},
#else
{
.name = "Fujitsu MB86900",
.iu_version = 0x00 << 24, /* Impl 0, ver 0 */
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
.mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
.mmu_bm = 0x00004000,
.mmu_ctpr_mask = 0x007ffff0,
.mmu_cxr_mask = 0x0000003f,
.mmu_sfsr_mask = 0xffffffff,
.mmu_trcr_mask = 0xffffffff,
.nwindows = 7,
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD,
},
{
.name = "Fujitsu MB86904",
.iu_version = 0x04 << 24, /* Impl 0, ver 4 */
@ -330,48 +317,6 @@ static const sparc_def_t sparc_defs[] = {
.nwindows = 8,
.features = CPU_DEFAULT_FEATURES,
},
{
.name = "LSI L64811",
.iu_version = 0x10 << 24, /* Impl 1, ver 0 */
.fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
.mmu_version = 0x10 << 24,
.mmu_bm = 0x00004000,
.mmu_ctpr_mask = 0x007ffff0,
.mmu_cxr_mask = 0x0000003f,
.mmu_sfsr_mask = 0xffffffff,
.mmu_trcr_mask = 0xffffffff,
.nwindows = 8,
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
CPU_FEATURE_FSMULD,
},
{
.name = "Cypress CY7C601",
.iu_version = 0x11 << 24, /* Impl 1, ver 1 */
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
.mmu_version = 0x10 << 24,
.mmu_bm = 0x00004000,
.mmu_ctpr_mask = 0x007ffff0,
.mmu_cxr_mask = 0x0000003f,
.mmu_sfsr_mask = 0xffffffff,
.mmu_trcr_mask = 0xffffffff,
.nwindows = 8,
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
CPU_FEATURE_FSMULD,
},
{
.name = "Cypress CY7C611",
.iu_version = 0x13 << 24, /* Impl 1, ver 3 */
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
.mmu_version = 0x10 << 24,
.mmu_bm = 0x00004000,
.mmu_ctpr_mask = 0x007ffff0,
.mmu_cxr_mask = 0x0000003f,
.mmu_sfsr_mask = 0xffffffff,
.mmu_trcr_mask = 0xffffffff,
.nwindows = 8,
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
CPU_FEATURE_FSMULD,
},
{
.name = "TI MicroSparc I",
.iu_version = 0x41000000,
@ -494,73 +439,6 @@ static const sparc_def_t sparc_defs[] = {
.nwindows = 8,
.features = CPU_DEFAULT_FEATURES,
},
{
.name = "Ross RT625",
.iu_version = 0x1e000000,
.fpu_version = 1 << 17,
.mmu_version = 0x1e000000,
.mmu_bm = 0x00004000,
.mmu_ctpr_mask = 0x007ffff0,
.mmu_cxr_mask = 0x0000003f,
.mmu_sfsr_mask = 0xffffffff,
.mmu_trcr_mask = 0xffffffff,
.nwindows = 8,
.features = CPU_DEFAULT_FEATURES,
},
{
.name = "Ross RT620",
.iu_version = 0x1f000000,
.fpu_version = 1 << 17,
.mmu_version = 0x1f000000,
.mmu_bm = 0x00004000,
.mmu_ctpr_mask = 0x007ffff0,
.mmu_cxr_mask = 0x0000003f,
.mmu_sfsr_mask = 0xffffffff,
.mmu_trcr_mask = 0xffffffff,
.nwindows = 8,
.features = CPU_DEFAULT_FEATURES,
},
{
.name = "BIT B5010",
.iu_version = 0x20000000,
.fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
.mmu_version = 0x20000000,
.mmu_bm = 0x00004000,
.mmu_ctpr_mask = 0x007ffff0,
.mmu_cxr_mask = 0x0000003f,
.mmu_sfsr_mask = 0xffffffff,
.mmu_trcr_mask = 0xffffffff,
.nwindows = 8,
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
CPU_FEATURE_FSMULD,
},
{
.name = "Matsushita MN10501",
.iu_version = 0x50000000,
.fpu_version = 0 << 17,
.mmu_version = 0x50000000,
.mmu_bm = 0x00004000,
.mmu_ctpr_mask = 0x007ffff0,
.mmu_cxr_mask = 0x0000003f,
.mmu_sfsr_mask = 0xffffffff,
.mmu_trcr_mask = 0xffffffff,
.nwindows = 8,
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT |
CPU_FEATURE_FSMULD,
},
{
.name = "Weitek W8601",
.iu_version = 0x90 << 24, /* Impl 9, ver 0 */
.fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
.mmu_version = 0x10 << 24,
.mmu_bm = 0x00004000,
.mmu_ctpr_mask = 0x007ffff0,
.mmu_cxr_mask = 0x0000003f,
.mmu_sfsr_mask = 0xffffffff,
.mmu_trcr_mask = 0xffffffff,
.nwindows = 8,
.features = CPU_DEFAULT_FEATURES,
},
{
.name = "LEON2",
.iu_version = 0xf2000000,