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consistent types for cpu_x86_fsave and cpu_x86_frstor

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3621 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard 2007-11-11 22:16:56 +00:00
parent 0d1e239407
commit 6f12a2a6ea
2 changed files with 6 additions and 6 deletions
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8
cpu-exec.c
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@ -751,26 +751,26 @@ void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
env = saved_env; env = saved_env;
} }
void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32)
{ {
CPUX86State *saved_env; CPUX86State *saved_env;
saved_env = env; saved_env = env;
env = s; env = s;
helper_fsave((target_ulong)(unsigned long)ptr, data32); helper_fsave(ptr, data32);
env = saved_env; env = saved_env;
} }
void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32)
{ {
CPUX86State *saved_env; CPUX86State *saved_env;
saved_env = env; saved_env = env;
env = s; env = s;
helper_frstor((target_ulong)(unsigned long)ptr, data32); helper_frstor(ptr, data32);
env = saved_env; env = saved_env;
} }

4
target-i386/cpu.h
View File

@ -670,8 +670,8 @@ CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
/* the following helpers are only usable in user mode simulation as /* the following helpers are only usable in user mode simulation as
they can trigger unexpected exceptions */ they can trigger unexpected exceptions */
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32); void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32); void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
/* you can call this signal handler from your SIGBUS and SIGSEGV /* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero signal handlers to inform the virtual CPU of exceptions. non zero