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Fix mulscc with high bits set in either src1 or src2

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5201 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2008-09-13 17:20:52 +00:00
parent 7c96d46ec2
commit 72ccba795b
1 changed files with 3 additions and 2 deletions
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5
target-sparc/translate.c
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@ -697,9 +697,9 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
if (!(env->y & 1)) if (!(env->y & 1))
T1 = 0; T1 = 0;
*/ */
tcg_gen_mov_tl(cpu_cc_src, src1); tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
tcg_gen_andi_tl(r_temp, cpu_y, 0x1); tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
tcg_gen_mov_tl(cpu_cc_src2, src2); tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1); tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
tcg_gen_movi_tl(cpu_cc_src2, 0); tcg_gen_movi_tl(cpu_cc_src2, 0);
gen_set_label(l1); gen_set_label(l1);
@ -709,6 +709,7 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1); tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
tcg_gen_shli_tl(r_temp, r_temp, 31); tcg_gen_shli_tl(r_temp, r_temp, 31);
tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1); tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1);
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x7fffffff);
tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp); tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp);
tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff); tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);