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intc/arm_gic: Implement virtualization extensions in gic_cpu_(read|write)

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Implement virtualization extensions in the gic_cpu_read() and
gic_cpu_write() functions. Those are the last bits missing to fully
support virtualization extensions in the CPU interface path.

Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180727095421.386-14-luc.michel@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Luc Michel 2018-08-14 17:17:20 +01:00 committed by Peter Maydell
parent 02f2e22d7c
commit 7eb079ec51
1 changed files with 15 additions and 5 deletions
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20
hw/intc/arm_gic.c
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@ -1401,9 +1401,12 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset,
case 0xd0: case 0xd4: case 0xd8: case 0xdc: case 0xd0: case 0xd4: case 0xd8: case 0xdc:
{ {
int regno = (offset - 0xd0) / 4; int regno = (offset - 0xd0) / 4;
int nr_aprs = gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS;
if (regno >= GIC_NR_APRS || s->revision != 2) { if (regno >= nr_aprs || s->revision != 2) {
*data = 0; *data = 0;
} else if (gic_is_vcpu(cpu)) {
*data = s->h_apr[gic_get_vcpu_real_id(cpu)];
} else if (gic_cpu_ns_access(s, cpu, attrs)) { } else if (gic_cpu_ns_access(s, cpu, attrs)) {
/* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
*data = gic_apr_ns_view(s, regno, cpu); *data = gic_apr_ns_view(s, regno, cpu);
@ -1417,7 +1420,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset,
int regno = (offset - 0xe0) / 4; int regno = (offset - 0xe0) / 4;
if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) || if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) ||
gic_cpu_ns_access(s, cpu, attrs)) { gic_cpu_ns_access(s, cpu, attrs) || gic_is_vcpu(cpu)) {
*data = 0; *data = 0;
} else { } else {
*data = s->nsapr[regno][cpu]; *data = s->nsapr[regno][cpu];
@ -1452,7 +1455,8 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset,
s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR);
} }
} else { } else {
s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); int min_bpr = gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR;
s->bpr[cpu] = MAX(value & 0x7, min_bpr);
} }
break; break;
case 0x10: /* End Of Interrupt */ case 0x10: /* End Of Interrupt */
@ -1469,11 +1473,14 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset,
case 0xd0: case 0xd4: case 0xd8: case 0xdc: case 0xd0: case 0xd4: case 0xd8: case 0xdc:
{ {
int regno = (offset - 0xd0) / 4; int regno = (offset - 0xd0) / 4;
int nr_aprs = gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS;
if (regno >= GIC_NR_APRS || s->revision != 2) { if (regno >= nr_aprs || s->revision != 2) {
return MEMTX_OK; return MEMTX_OK;
} }
if (gic_cpu_ns_access(s, cpu, attrs)) { if (gic_is_vcpu(cpu)) {
s->h_apr[gic_get_vcpu_real_id(cpu)] = value;
} else if (gic_cpu_ns_access(s, cpu, attrs)) {
/* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */ /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
gic_apr_write_ns_view(s, regno, cpu, value); gic_apr_write_ns_view(s, regno, cpu, value);
} else { } else {
@ -1488,6 +1495,9 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset,
if (regno >= GIC_NR_APRS || s->revision != 2) { if (regno >= GIC_NR_APRS || s->revision != 2) {
return MEMTX_OK; return MEMTX_OK;
} }
if (gic_is_vcpu(cpu)) {
return MEMTX_OK;
}
if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) {
return MEMTX_OK; return MEMTX_OK;
} }