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target/arm: Add ID_ISAR6

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This register was added to aa32 state by ARMv8.2.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180629001538.11415-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2018-06-28 17:15:37 -07:00 committed by Peter Maydell
parent 0b33968e7f
commit 802abf4024
4 changed files with 9 additions and 3 deletions
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4
target/arm/cpu.c
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@ -1273,6 +1273,7 @@ static void cortex_m3_initfn(Object *obj)
cpu->id_isar3 = 0x01111110; cpu->id_isar3 = 0x01111110;
cpu->id_isar4 = 0x01310102; cpu->id_isar4 = 0x01310102;
cpu->id_isar5 = 0x00000000; cpu->id_isar5 = 0x00000000;
cpu->id_isar6 = 0x00000000;
} }
static void cortex_m4_initfn(Object *obj) static void cortex_m4_initfn(Object *obj)
@ -1299,6 +1300,7 @@ static void cortex_m4_initfn(Object *obj)
cpu->id_isar3 = 0x01111110; cpu->id_isar3 = 0x01111110;
cpu->id_isar4 = 0x01310102; cpu->id_isar4 = 0x01310102;
cpu->id_isar5 = 0x00000000; cpu->id_isar5 = 0x00000000;
cpu->id_isar6 = 0x00000000;
} }
static void cortex_m33_initfn(Object *obj) static void cortex_m33_initfn(Object *obj)
@ -1327,6 +1329,7 @@ static void cortex_m33_initfn(Object *obj)
cpu->id_isar3 = 0x01111131; cpu->id_isar3 = 0x01111131;
cpu->id_isar4 = 0x01310132; cpu->id_isar4 = 0x01310132;
cpu->id_isar5 = 0x00000000; cpu->id_isar5 = 0x00000000;
cpu->id_isar6 = 0x00000000;
cpu->clidr = 0x00000000; cpu->clidr = 0x00000000;
cpu->ctr = 0x8000c000; cpu->ctr = 0x8000c000;
} }
@ -1377,6 +1380,7 @@ static void cortex_r5_initfn(Object *obj)
cpu->id_isar3 = 0x01112131; cpu->id_isar3 = 0x01112131;
cpu->id_isar4 = 0x0010142; cpu->id_isar4 = 0x0010142;
cpu->id_isar5 = 0x0; cpu->id_isar5 = 0x0;
cpu->id_isar6 = 0x0;
cpu->mp_is_up = true; cpu->mp_is_up = true;
cpu->pmsav7_dregion = 16; cpu->pmsav7_dregion = 16;
define_arm_cp_regs(cpu, cortexr5_cp_reginfo); define_arm_cp_regs(cpu, cortexr5_cp_reginfo);

1
target/arm/cpu.h
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@ -813,6 +813,7 @@ struct ARMCPU {
uint32_t id_isar3; uint32_t id_isar3;
uint32_t id_isar4; uint32_t id_isar4;
uint32_t id_isar5; uint32_t id_isar5;
uint32_t id_isar6;
uint64_t id_aa64pfr0; uint64_t id_aa64pfr0;
uint64_t id_aa64pfr1; uint64_t id_aa64pfr1;
uint64_t id_aa64dfr0; uint64_t id_aa64dfr0;

2
target/arm/cpu64.c
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@ -139,6 +139,7 @@ static void aarch64_a57_initfn(Object *obj)
cpu->id_isar3 = 0x01112131; cpu->id_isar3 = 0x01112131;
cpu->id_isar4 = 0x00011142; cpu->id_isar4 = 0x00011142;
cpu->id_isar5 = 0x00011121; cpu->id_isar5 = 0x00011121;
cpu->id_isar6 = 0;
cpu->id_aa64pfr0 = 0x00002222; cpu->id_aa64pfr0 = 0x00002222;
cpu->id_aa64dfr0 = 0x10305106; cpu->id_aa64dfr0 = 0x10305106;
cpu->pmceid0 = 0x00000000; cpu->pmceid0 = 0x00000000;
@ -199,6 +200,7 @@ static void aarch64_a53_initfn(Object *obj)
cpu->id_isar3 = 0x01112131; cpu->id_isar3 = 0x01112131;
cpu->id_isar4 = 0x00011142; cpu->id_isar4 = 0x00011142;
cpu->id_isar5 = 0x00011121; cpu->id_isar5 = 0x00011121;
cpu->id_isar6 = 0;
cpu->id_aa64pfr0 = 0x00002222; cpu->id_aa64pfr0 = 0x00002222;
cpu->id_aa64dfr0 = 0x10305106; cpu->id_aa64dfr0 = 0x10305106;
cpu->id_aa64isar0 = 0x00011120; cpu->id_aa64isar0 = 0x00011120;

5
target/arm/helper.c
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@ -4872,11 +4872,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST, .access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = cpu->id_mmfr4 }, .resetvalue = cpu->id_mmfr4 },
/* 7 is as yet unallocated and must RAZ */ { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
{ .name = "ID_ISAR7_RESERVED", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST, .access = PL1_R, .type = ARM_CP_CONST,
.resetvalue = 0 }, .resetvalue = cpu->id_isar6 },
REGINFO_SENTINEL REGINFO_SENTINEL
}; };
define_arm_cp_regs(cpu, v6_idregs); define_arm_cp_regs(cpu, v6_idregs);