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target-alpha: Split up FPCR value into separate fields.

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The fpcr_exc_status, fpcr_exc_mask, and fpcr_dyn_round fields
are stored in <softfloat.h> format for convenience during
regular execution.

Revert the addition of float_exception_mask to float_status,
added in ba0e276db4b51bd2255a5d5ff8902c70d32ade40.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Richard Henderson 2009-12-31 12:41:07 -08:00 committed by Aurelien Jarno
parent 7c5a90dd41
commit 8443effb50
3 changed files with 125 additions and 55 deletions
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1
fpu/softfloat.h
View File

@ -187,7 +187,6 @@ typedef struct float_status {
signed char float_detect_tininess; signed char float_detect_tininess;
signed char float_rounding_mode; signed char float_rounding_mode;
signed char float_exception_flags; signed char float_exception_flags;
signed char float_exception_mask;
#ifdef FLOATX80 #ifdef FLOATX80
signed char floatx80_rounding_precision; signed char floatx80_rounding_precision;
#endif #endif

24
target-alpha/cpu.h
View File

@ -145,6 +145,10 @@ enum {
#define FPCR_UNFD (1ULL << 61) #define FPCR_UNFD (1ULL << 61)
#define FPCR_UNDZ (1ULL << 60) #define FPCR_UNDZ (1ULL << 60)
#define FPCR_DYN_SHIFT 58 #define FPCR_DYN_SHIFT 58
#define FPCR_DYN_CHOPPED (0ULL << FPCR_DYN_SHIFT)
#define FPCR_DYN_MINUS (1ULL << FPCR_DYN_SHIFT)
#define FPCR_DYN_NORMAL (2ULL << FPCR_DYN_SHIFT)
#define FPCR_DYN_PLUS (3ULL << FPCR_DYN_SHIFT)
#define FPCR_DYN_MASK (3ULL << FPCR_DYN_SHIFT) #define FPCR_DYN_MASK (3ULL << FPCR_DYN_SHIFT)
#define FPCR_IOV (1ULL << 57) #define FPCR_IOV (1ULL << 57)
#define FPCR_INE (1ULL << 56) #define FPCR_INE (1ULL << 56)
@ -341,17 +345,27 @@ struct pal_handler_t {
struct CPUAlphaState { struct CPUAlphaState {
uint64_t ir[31]; uint64_t ir[31];
float64 fir[31]; float64 fir[31];
float_status fp_status;
uint64_t fpcr;
uint64_t pc; uint64_t pc;
uint64_t lock; uint64_t lock;
uint32_t pcc[2]; uint32_t pcc[2];
uint64_t ipr[IPR_LAST]; uint64_t ipr[IPR_LAST];
uint64_t ps; uint64_t ps;
uint64_t unique; uint64_t unique;
int saved_mode; /* Used for HW_LD / HW_ST */ float_status fp_status;
int intr_flag; /* For RC and RS */ /* The following fields make up the FPCR, but in FP_STATUS format. */
uint8_t fpcr_exc_status;
uint8_t fpcr_exc_mask;
uint8_t fpcr_dyn_round;
uint8_t fpcr_flush_to_zero;
uint8_t fpcr_dnz;
uint8_t fpcr_dnod;
uint8_t fpcr_undz;
/* Used for HW_LD / HW_ST */
uint8_t saved_mode;
/* For RC and RS */
uint8_t intr_flag;
#if TARGET_LONG_BITS > HOST_LONG_BITS #if TARGET_LONG_BITS > HOST_LONG_BITS
/* temporary fixed-point registers /* temporary fixed-point registers

155
target-alpha/helper.c
View File

@ -27,79 +27,136 @@
uint64_t cpu_alpha_load_fpcr (CPUState *env) uint64_t cpu_alpha_load_fpcr (CPUState *env)
{ {
uint64_t ret = 0; uint64_t r = 0;
int flags, mask; uint8_t t;
flags = env->fp_status.float_exception_flags; t = env->fpcr_exc_status;
ret |= (uint64_t) flags << 52; if (t) {
if (flags) r = FPCR_SUM;
ret |= FPCR_SUM; if (t & float_flag_invalid) {
env->ipr[IPR_EXC_SUM] &= ~0x3E; r |= FPCR_INV;
env->ipr[IPR_EXC_SUM] |= flags << 1; }
if (t & float_flag_divbyzero) {
r |= FPCR_DZE;
}
if (t & float_flag_overflow) {
r |= FPCR_OVF;
}
if (t & float_flag_underflow) {
r |= FPCR_UNF;
}
if (t & float_flag_inexact) {
r |= FPCR_INE;
}
}
mask = env->fp_status.float_exception_mask; t = env->fpcr_exc_mask;
if (mask & float_flag_invalid) if (t & float_flag_invalid) {
ret |= FPCR_INVD; r |= FPCR_INVD;
if (mask & float_flag_divbyzero) }
ret |= FPCR_DZED; if (t & float_flag_divbyzero) {
if (mask & float_flag_overflow) r |= FPCR_DZED;
ret |= FPCR_OVFD; }
if (mask & float_flag_underflow) if (t & float_flag_overflow) {
ret |= FPCR_UNFD; r |= FPCR_OVFD;
if (mask & float_flag_inexact) }
ret |= FPCR_INED; if (t & float_flag_underflow) {
r |= FPCR_UNFD;
}
if (t & float_flag_inexact) {
r |= FPCR_INED;
}
switch (env->fp_status.float_rounding_mode) { switch (env->fpcr_dyn_round) {
case float_round_nearest_even: case float_round_nearest_even:
ret |= 2ULL << FPCR_DYN_SHIFT; r |= FPCR_DYN_NORMAL;
break; break;
case float_round_down: case float_round_down:
ret |= 1ULL << FPCR_DYN_SHIFT; r |= FPCR_DYN_MINUS;
break; break;
case float_round_up: case float_round_up:
ret |= 3ULL << FPCR_DYN_SHIFT; r |= FPCR_DYN_PLUS;
break; break;
case float_round_to_zero: case float_round_to_zero:
r |= FPCR_DYN_CHOPPED;
break; break;
} }
return ret;
if (env->fpcr_dnz) {
r |= FPCR_DNZ;
}
if (env->fpcr_dnod) {
r |= FPCR_DNOD;
}
if (env->fpcr_undz) {
r |= FPCR_UNDZ;
}
return r;
} }
void cpu_alpha_store_fpcr (CPUState *env, uint64_t val) void cpu_alpha_store_fpcr (CPUState *env, uint64_t val)
{ {
int round_mode, mask; uint8_t t;
set_float_exception_flags((val >> 52) & 0x3F, &env->fp_status); t = 0;
if (val & FPCR_INV) {
t |= float_flag_invalid;
}
if (val & FPCR_DZE) {
t |= float_flag_divbyzero;
}
if (val & FPCR_OVF) {
t |= float_flag_overflow;
}
if (val & FPCR_UNF) {
t |= float_flag_underflow;
}
if (val & FPCR_INE) {
t |= float_flag_inexact;
}
env->fpcr_exc_status = t;
mask = 0; t = 0;
if (val & FPCR_INVD) if (val & FPCR_INVD) {
mask |= float_flag_invalid; t |= float_flag_invalid;
if (val & FPCR_DZED) }
mask |= float_flag_divbyzero; if (val & FPCR_DZED) {
if (val & FPCR_OVFD) t |= float_flag_divbyzero;
mask |= float_flag_overflow; }
if (val & FPCR_UNFD) if (val & FPCR_OVFD) {
mask |= float_flag_underflow; t |= float_flag_overflow;
if (val & FPCR_INED) }
mask |= float_flag_inexact; if (val & FPCR_UNFD) {
env->fp_status.float_exception_mask = mask; t |= float_flag_underflow;
}
if (val & FPCR_INED) {
t |= float_flag_inexact;
}
env->fpcr_exc_mask = t;
switch ((val >> FPCR_DYN_SHIFT) & 3) { switch (val & FPCR_DYN_MASK) {
case 0: case FPCR_DYN_CHOPPED:
round_mode = float_round_to_zero; t = float_round_to_zero;
break; break;
case 1: case FPCR_DYN_MINUS:
round_mode = float_round_down; t = float_round_down;
break; break;
case 2: case FPCR_DYN_NORMAL:
round_mode = float_round_nearest_even; t = float_round_nearest_even;
break; break;
case 3: case FPCR_DYN_PLUS:
default: /* this avoids a gcc (< 4.4) warning */ t = float_round_up;
round_mode = float_round_up;
break; break;
} }
set_float_rounding_mode(round_mode, &env->fp_status); env->fpcr_dyn_round = t;
env->fpcr_flush_to_zero
= (val & (FPCR_UNDZ|FPCR_UNFD)) == (FPCR_UNDZ|FPCR_UNFD);
env->fpcr_dnz = (val & FPCR_DNZ) != 0;
env->fpcr_dnod = (val & FPCR_DNOD) != 0;
env->fpcr_undz = (val & FPCR_UNDZ) != 0;
} }
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)