spapr_pci: QOM'ify sPAPR PCI host bridge
Introduce type constant. Introduce cast macro to drop bogus busdev field that would've broken SYS_BUS_DEVICE(). Avoid accessing parent fields directly. Free the identifier phb as acronym for PCI_HOST_BRIDGE. Updated against conflicting merge from branch 'agraf/ppc-for-upstream' (0d16fdd732d1b211842fa96b7c90ddf9e6bde0e4), which removed busdev field differently, moved some code around and added new occurrences of 'phb'. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Andreas Färber
Anthony Liguori
parent
03a6b66770
commit
8c9f64df3d
@ -612,6 +612,7 @@ static void ppc_spapr_init(ram_addr_t ram_size,
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{
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PowerPCCPU *cpu;
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CPUPPCState *env;
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PCIHostState *phb;
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int i;
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MemoryRegion *sysmem = get_system_memory();
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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@ -742,6 +743,7 @@ static void ppc_spapr_init(ram_addr_t ram_size,
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SPAPR_PCI_MEM_WIN_SIZE,
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SPAPR_PCI_IO_WIN_ADDR,
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SPAPR_PCI_MSI_WIN_ADDR);
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phb = &QLIST_FIRST(&spapr->phbs)->host_state;
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for (i = 0; i < nb_nics; i++) {
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NICInfo *nd = &nd_table[i];
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@ -762,13 +764,12 @@ static void ppc_spapr_init(ram_addr_t ram_size,
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}
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/* Graphics */
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if (spapr_vga_init(QLIST_FIRST(&spapr->phbs)->host_state.bus)) {
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if (spapr_vga_init(phb->bus)) {
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spapr->has_graphics = true;
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}
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if (usb_enabled) {
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pci_create_simple(QLIST_FIRST(&spapr->phbs)->host_state.bus,
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-1, "pci-ohci");
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pci_create_simple(phb->bus, -1, "pci-ohci");
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if (spapr->has_graphics) {
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usbdevice_create("keyboard");
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usbdevice_create("mouse");
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@ -48,13 +48,13 @@
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static sPAPRPHBState *find_phb(sPAPREnvironment *spapr, uint64_t buid)
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{
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sPAPRPHBState *phb;
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sPAPRPHBState *sphb;
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QLIST_FOREACH(phb, &spapr->phbs, list) {
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if (phb->buid != buid) {
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QLIST_FOREACH(sphb, &spapr->phbs, list) {
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if (sphb->buid != buid) {
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continue;
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}
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return phb;
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return sphb;
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}
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return NULL;
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@ -63,7 +63,9 @@ static sPAPRPHBState *find_phb(sPAPREnvironment *spapr, uint64_t buid)
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static PCIDevice *find_dev(sPAPREnvironment *spapr, uint64_t buid,
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uint32_t config_addr)
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{
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sPAPRPHBState *phb = find_phb(spapr, buid);
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sPAPRPHBState *sphb = find_phb(spapr, buid);
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PCIHostState *phb = &sphb->host_state;
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BusState *bus = BUS(phb->bus);
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BusChild *kid;
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int devfn = (config_addr >> 8) & 0xFF;
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@ -71,7 +73,7 @@ static PCIDevice *find_dev(sPAPREnvironment *spapr, uint64_t buid,
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return NULL;
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}
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QTAILQ_FOREACH(kid, &phb->host_state.bus->qbus.children, sibling) {
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QTAILQ_FOREACH(kid, &bus->children, sibling) {
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PCIDevice *dev = (PCIDevice *)kid->child;
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if (dev->devfn == devfn) {
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return dev;
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@ -514,23 +516,24 @@ static DMAContext *spapr_pci_dma_context_fn(PCIBus *bus, void *opaque,
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static int spapr_phb_init(SysBusDevice *s)
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{
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sPAPRPHBState *phb = DO_UPCAST(sPAPRPHBState, host_state.busdev, s);
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sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
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PCIHostState *phb = FROM_SYSBUS(PCIHostState, s);
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char *namebuf;
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int i;
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PCIBus *bus;
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phb->dtbusname = g_strdup_printf("pci@%" PRIx64, phb->buid);
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namebuf = alloca(strlen(phb->dtbusname) + 32);
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sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid);
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namebuf = alloca(strlen(sphb->dtbusname) + 32);
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/* Initialize memory regions */
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sprintf(namebuf, "%s.mmio", phb->dtbusname);
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memory_region_init(&phb->memspace, namebuf, INT64_MAX);
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sprintf(namebuf, "%s.mmio", sphb->dtbusname);
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memory_region_init(&sphb->memspace, namebuf, INT64_MAX);
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sprintf(namebuf, "%s.mmio-alias", phb->dtbusname);
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memory_region_init_alias(&phb->memwindow, namebuf, &phb->memspace,
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SPAPR_PCI_MEM_WIN_BUS_OFFSET, phb->mem_win_size);
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memory_region_add_subregion(get_system_memory(), phb->mem_win_addr,
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&phb->memwindow);
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sprintf(namebuf, "%s.mmio-alias", sphb->dtbusname);
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memory_region_init_alias(&sphb->memwindow, namebuf, &sphb->memspace,
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SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size);
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memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr,
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&sphb->memwindow);
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/* On ppc, we only have MMIO no specific IO space from the CPU
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* perspective. In theory we ought to be able to embed the PCI IO
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@ -540,42 +543,42 @@ static int spapr_phb_init(SysBusDevice *s)
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* system io address space. This hack to bounce things via
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* system_io works around the problem until all the users of
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* old_portion are updated */
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sprintf(namebuf, "%s.io", phb->dtbusname);
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memory_region_init(&phb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE);
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sprintf(namebuf, "%s.io", sphb->dtbusname);
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memory_region_init(&sphb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE);
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/* FIXME: fix to support multiple PHBs */
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memory_region_add_subregion(get_system_io(), 0, &phb->iospace);
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memory_region_add_subregion(get_system_io(), 0, &sphb->iospace);
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sprintf(namebuf, "%s.io-alias", phb->dtbusname);
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memory_region_init_io(&phb->iowindow, &spapr_io_ops, phb,
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sprintf(namebuf, "%s.io-alias", sphb->dtbusname);
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memory_region_init_io(&sphb->iowindow, &spapr_io_ops, sphb,
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namebuf, SPAPR_PCI_IO_WIN_SIZE);
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memory_region_add_subregion(get_system_memory(), phb->io_win_addr,
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&phb->iowindow);
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memory_region_add_subregion(get_system_memory(), sphb->io_win_addr,
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&sphb->iowindow);
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/* As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
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* we need to allocate some memory to catch those writes coming
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* from msi_notify()/msix_notify() */
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if (msi_supported) {
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sprintf(namebuf, "%s.msi", phb->dtbusname);
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memory_region_init_io(&phb->msiwindow, &spapr_msi_ops, phb,
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sprintf(namebuf, "%s.msi", sphb->dtbusname);
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memory_region_init_io(&sphb->msiwindow, &spapr_msi_ops, sphb,
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namebuf, SPAPR_MSIX_MAX_DEVS * 0x10000);
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memory_region_add_subregion(get_system_memory(), phb->msi_win_addr,
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&phb->msiwindow);
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memory_region_add_subregion(get_system_memory(), sphb->msi_win_addr,
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&sphb->msiwindow);
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}
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bus = pci_register_bus(&phb->host_state.busdev.qdev,
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phb->busname ? phb->busname : phb->dtbusname,
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pci_spapr_set_irq, pci_spapr_map_irq, phb,
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&phb->memspace, &phb->iospace,
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bus = pci_register_bus(DEVICE(s),
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sphb->busname ? sphb->busname : sphb->dtbusname,
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pci_spapr_set_irq, pci_spapr_map_irq, sphb,
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&sphb->memspace, &sphb->iospace,
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PCI_DEVFN(0, 0), PCI_NUM_PINS);
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phb->host_state.bus = bus;
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phb->bus = bus;
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phb->dma_liobn = SPAPR_PCI_BASE_LIOBN | (pci_find_domain(bus) << 16);
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phb->dma_window_start = 0;
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phb->dma_window_size = 0x40000000;
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phb->dma = spapr_tce_new_dma_context(phb->dma_liobn, phb->dma_window_size);
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pci_setup_iommu(bus, spapr_pci_dma_context_fn, phb);
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sphb->dma_liobn = SPAPR_PCI_BASE_LIOBN | (pci_find_domain(bus) << 16);
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sphb->dma_window_start = 0;
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sphb->dma_window_size = 0x40000000;
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sphb->dma = spapr_tce_new_dma_context(sphb->dma_liobn, sphb->dma_window_size);
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pci_setup_iommu(bus, spapr_pci_dma_context_fn, sphb);
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QLIST_INSERT_HEAD(&spapr->phbs, phb, list);
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QLIST_INSERT_HEAD(&spapr->phbs, sphb, list);
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/* Initialize the LSI table */
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for (i = 0; i < PCI_NUM_PINS; i++) {
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@ -586,7 +589,7 @@ static int spapr_phb_init(SysBusDevice *s)
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return -1;
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}
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phb->lsi_table[i].irq = irq;
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sphb->lsi_table[i].irq = irq;
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}
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return 0;
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@ -613,7 +616,7 @@ static void spapr_phb_class_init(ObjectClass *klass, void *data)
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}
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static const TypeInfo spapr_phb_info = {
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.name = "spapr-pci-host-bridge",
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.name = TYPE_SPAPR_PCI_HOST_BRIDGE,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(sPAPRPHBState),
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.class_init = spapr_phb_class_init,
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@ -626,7 +629,7 @@ void spapr_create_phb(sPAPREnvironment *spapr,
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{
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DeviceState *dev;
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dev = qdev_create(NULL, spapr_phb_info.name);
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dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
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if (busname) {
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qdev_prop_set_string(dev, "busname", g_strdup(busname));
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@ -750,8 +753,9 @@ void spapr_pci_rtas_init(void)
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}
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}
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static void register_types(void)
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static void spapr_pci_register_types(void)
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{
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type_register_static(&spapr_phb_info);
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}
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type_init(register_types)
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type_init(spapr_pci_register_types)
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@ -29,6 +29,11 @@
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#define SPAPR_MSIX_MAX_DEVS 32
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#define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
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#define SPAPR_PCI_HOST_BRIDGE(obj) \
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OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
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typedef struct sPAPRPHBState {
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PCIHostState host_state;
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