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sun4u: implement interrupt clearing registers

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Implement registers for clearing OBIO and PCI interrupts

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Artyom Tarasenko 2012-05-12 11:15:23 +02:00 committed by Blue Swirl
parent d1d80055ba
commit 94d1991445
1 changed files with 12 additions and 0 deletions
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12
hw/apb_pci.c
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@ -85,6 +85,8 @@ typedef struct APBState {
unsigned int nr_resets; unsigned int nr_resets;
} APBState; } APBState;
static void pci_apb_set_irq(void *opaque, int irq_num, int level);
static void apb_config_writel (void *opaque, target_phys_addr_t addr, static void apb_config_writel (void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size) uint64_t val, unsigned size)
{ {
@ -113,6 +115,16 @@ static void apb_config_writel (void *opaque, target_phys_addr_t addr,
s->obio_irq_map[(addr & 0xff) >> 3] |= val & ~PBM_PCI_IMR_MASK; s->obio_irq_map[(addr & 0xff) >> 3] |= val & ~PBM_PCI_IMR_MASK;
} }
break; break;
case 0x1400 ... 0x143f: /* PCI interrupt clear */
if (addr & 4) {
pci_apb_set_irq(s, (addr & 0x3f) >> 3, 0);
}
break;
case 0x1800 ... 0x1860: /* OBIO interrupt clear */
if (addr & 4) {
pci_apb_set_irq(s, 0x20 | ((addr & 0xff) >> 3), 0);
}
break;
case 0x2000 ... 0x202f: /* PCI control */ case 0x2000 ... 0x202f: /* PCI control */
s->pci_control[(addr & 0x3f) >> 2] = val; s->pci_control[(addr & 0x3f) >> 2] = val;
break; break;