david.venhoff/QEMU-Nyx-fork
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Simplify some constant loads

Browse Source 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4383 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2008-05-07 18:04:29 +00:00
parent ba28189bac
commit 9c6c6662d1
1 changed files with 14 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
target-sparc/translate.c
View File

@ -1909,8 +1909,7 @@ static void disas_sparc_insn(DisasContext * dc)
case 0x4: /* SETHI */ case 0x4: /* SETHI */
if (rd) { // nop if (rd) { // nop
uint32_t value = GET_FIELD(insn, 10, 31); uint32_t value = GET_FIELD(insn, 10, 31);
tcg_gen_movi_tl(cpu_dst, value << 10); gen_movl_TN_reg(rd, tcg_const_tl(value << 10));
gen_movl_TN_reg(rd, cpu_dst);
} }
break; break;
case 0x0: /* UNIMPL */ case 0x0: /* UNIMPL */
@ -2015,8 +2014,7 @@ static void disas_sparc_insn(DisasContext * dc)
} }
break; break;
case 0x5: /* V9 rdpc */ case 0x5: /* V9 rdpc */
tcg_gen_movi_tl(cpu_dst, dc->pc); gen_movl_TN_reg(rd, tcg_const_tl(dc->pc));
gen_movl_TN_reg(rd, cpu_dst);
break; break;
case 0x6: /* V9 rdfprs */ case 0x6: /* V9 rdfprs */
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs)); tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
@ -2821,27 +2819,29 @@ static void disas_sparc_insn(DisasContext * dc)
// or %g0, x, y -> mov T0, x; mov y, T0 // or %g0, x, y -> mov T0, x; mov y, T0
if (IS_IMM) { /* immediate */ if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 19, 31); rs2 = GET_FIELDs(insn, 19, 31);
tcg_gen_movi_tl(cpu_dst, (int)rs2); gen_movl_TN_reg(rd, tcg_const_tl((int)rs2));
} else { /* register */ } else { /* register */
rs2 = GET_FIELD(insn, 27, 31); rs2 = GET_FIELD(insn, 27, 31);
gen_movl_reg_TN(rs2, cpu_dst); gen_movl_reg_TN(rs2, cpu_dst);
gen_movl_TN_reg(rd, cpu_dst);
} }
} else { } else {
cpu_src1 = get_src1(insn, cpu_src1); cpu_src1 = get_src1(insn, cpu_src1);
if (IS_IMM) { /* immediate */ if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 19, 31); rs2 = GET_FIELDs(insn, 19, 31);
tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2); tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
gen_movl_TN_reg(rd, cpu_dst);
} else { /* register */ } else { /* register */
// or x, %g0, y -> mov T1, x; mov y, T1 // or x, %g0, y -> mov T1, x; mov y, T1
rs2 = GET_FIELD(insn, 27, 31); rs2 = GET_FIELD(insn, 27, 31);
if (rs2 != 0) { if (rs2 != 0) {
gen_movl_reg_TN(rs2, cpu_src2); gen_movl_reg_TN(rs2, cpu_src2);
tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
} else
tcg_gen_mov_tl(cpu_dst, cpu_src1);
}
}
gen_movl_TN_reg(rd, cpu_dst); gen_movl_TN_reg(rd, cpu_dst);
} else
gen_movl_TN_reg(rd, cpu_src1);
}
}
#ifdef TARGET_SPARC64 #ifdef TARGET_SPARC64
} else if (xop == 0x25) { /* sll, V9 sllx */ } else if (xop == 0x25) { /* sll, V9 sllx */
cpu_src1 = get_src1(insn, cpu_src1); cpu_src1 = get_src1(insn, cpu_src1);
@ -3405,12 +3405,12 @@ static void disas_sparc_insn(DisasContext * dc)
tcg_const_tl(0), l1); tcg_const_tl(0), l1);
if (IS_IMM) { /* immediate */ if (IS_IMM) { /* immediate */
rs2 = GET_FIELD_SPs(insn, 0, 10); rs2 = GET_FIELD_SPs(insn, 0, 10);
tcg_gen_movi_tl(cpu_dst, (int)rs2); gen_movl_TN_reg(rd, tcg_const_tl((int)rs2));
} else { } else {
rs2 = GET_FIELD_SP(insn, 0, 4); rs2 = GET_FIELD_SP(insn, 0, 4);
gen_movl_reg_TN(rs2, cpu_dst); gen_movl_reg_TN(rs2, cpu_tmp0);
gen_movl_TN_reg(rd, cpu_tmp0);
} }
gen_movl_TN_reg(rd, cpu_dst);
gen_set_label(l1); gen_set_label(l1);
break; break;
} }
@ -3438,12 +3438,12 @@ static void disas_sparc_insn(DisasContext * dc)
tcg_const_tl(0), l1); tcg_const_tl(0), l1);
if (IS_IMM) { /* immediate */ if (IS_IMM) { /* immediate */
rs2 = GET_FIELD_SPs(insn, 0, 9); rs2 = GET_FIELD_SPs(insn, 0, 9);
tcg_gen_movi_tl(cpu_dst, (int)rs2); gen_movl_TN_reg(rd, tcg_const_tl((int)rs2));
} else { } else {
rs2 = GET_FIELD_SP(insn, 0, 4); rs2 = GET_FIELD_SP(insn, 0, 4);
gen_movl_reg_TN(rs2, cpu_dst); gen_movl_reg_TN(rs2, cpu_tmp0);
gen_movl_TN_reg(rd, cpu_tmp0);
} }
gen_movl_TN_reg(rd, cpu_dst);
gen_set_label(l1); gen_set_label(l1);
break; break;
} }
@ -3900,10 +3900,7 @@ static void disas_sparc_insn(DisasContext * dc)
switch (xop) { switch (xop) {
case 0x38: /* jmpl */ case 0x38: /* jmpl */
{ {
if (rd != 0) { gen_movl_TN_reg(rd, tcg_const_tl(dc->pc));
tcg_gen_movi_tl(cpu_tmp0, dc->pc);
gen_movl_TN_reg(rd, cpu_tmp0);
}
gen_mov_pc_npc(dc, cpu_cond); gen_mov_pc_npc(dc, cpu_cond);
tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3)); tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
tcg_gen_mov_tl(cpu_npc, cpu_dst); tcg_gen_mov_tl(cpu_npc, cpu_dst);