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hw/pxa2xx_pic: Convert coprocessor registers to new scheme

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Convert the coprocessor access functions for the pxa2xx PIC to the
arm_cp_reginfo scheme.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2012-06-20 11:57:08 +00:00
parent e2f8a44d0d
commit 9ee703b096
1 changed files with 31 additions and 22 deletions
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51
hw/pxa2xx_pic.c
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@ -209,33 +209,42 @@ static const int pxa2xx_cp_reg_map[0x10] = {
[0xa] = ICPR2, [0xa] = ICPR2,
}; };
static uint32_t pxa2xx_pic_cp_read(void *opaque, int op2, int reg, int crm) static int pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t *value)
{ {
target_phys_addr_t offset; int offset = pxa2xx_cp_reg_map[ri->crn];
*value = pxa2xx_pic_mem_read(ri->opaque, offset, 4);
if (pxa2xx_cp_reg_map[reg] == -1) {
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
return 0; return 0;
}
offset = pxa2xx_cp_reg_map[reg];
return pxa2xx_pic_mem_read(opaque, offset, 4);
} }
static void pxa2xx_pic_cp_write(void *opaque, int op2, int reg, int crm, static int pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint32_t value) uint64_t value)
{ {
target_phys_addr_t offset; int offset = pxa2xx_cp_reg_map[ri->crn];
pxa2xx_pic_mem_write(ri->opaque, offset, value, 4);
if (pxa2xx_cp_reg_map[reg] == -1) { return 0;
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
return;
}
offset = pxa2xx_cp_reg_map[reg];
pxa2xx_pic_mem_write(opaque, offset, value, 4);
} }
#define REGINFO_FOR_PIC_CP(NAME, CRN) \
{ .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \
.access = PL1_RW, \
.readfn = pxa2xx_pic_cp_read, .writefn = pxa2xx_pic_cp_write }
static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
REGINFO_FOR_PIC_CP("ICIP", 0),
REGINFO_FOR_PIC_CP("ICMR", 1),
REGINFO_FOR_PIC_CP("ICLR", 2),
REGINFO_FOR_PIC_CP("ICFP", 3),
REGINFO_FOR_PIC_CP("ICPR", 4),
REGINFO_FOR_PIC_CP("ICHP", 5),
REGINFO_FOR_PIC_CP("ICIP2", 6),
REGINFO_FOR_PIC_CP("ICMR2", 7),
REGINFO_FOR_PIC_CP("ICLR2", 8),
REGINFO_FOR_PIC_CP("ICFP2", 9),
REGINFO_FOR_PIC_CP("ICPR2", 0xa),
REGINFO_SENTINEL
};
static const MemoryRegionOps pxa2xx_pic_ops = { static const MemoryRegionOps pxa2xx_pic_ops = {
.read = pxa2xx_pic_mem_read, .read = pxa2xx_pic_mem_read,
.write = pxa2xx_pic_mem_write, .write = pxa2xx_pic_mem_write,
@ -274,7 +283,7 @@ DeviceState *pxa2xx_pic_init(target_phys_addr_t base, ARMCPU *cpu)
sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
/* Enable IC coprocessor access. */ /* Enable IC coprocessor access. */
cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, s); define_arm_cp_regs_with_opaque(arm_env_get_cpu(env), pxa_pic_cp_reginfo, s);
return dev; return dev;
} }