target-tilegx: Add cpu basic features for linux-user
It implements minimized cpu features for linux-user. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <BLU436-SMTP114819BB03D853801AA9C3CB9660@phx.gbl> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Chen Gang
Richard Henderson
parent
b69773a8a7
commit
9f64170df2
170
target-tilegx/cpu.c
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170
target-tilegx/cpu.c
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/*
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* QEMU TILE-Gx CPU
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*
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* Copyright (c) 2015 Chen Gang
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "cpu.h"
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#include "qemu-common.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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static void tilegx_cpu_dump_state(CPUState *cs, FILE *f,
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fprintf_function cpu_fprintf, int flags)
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{
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static const char * const reg_names[TILEGX_R_COUNT] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
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"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
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"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
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"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
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"r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr"
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};
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TileGXCPU *cpu = TILEGX_CPU(cs);
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CPUTLGState *env = &cpu->env;
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int i;
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for (i = 0; i < TILEGX_R_COUNT; i++) {
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cpu_fprintf(f, "%-4s" TARGET_FMT_lx "%s",
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reg_names[i], env->regs[i],
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(i % 4) == 3 ? "\n" : " ");
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}
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cpu_fprintf(f, "PC " TARGET_FMT_lx " CEX " TARGET_FMT_lx "\n\n",
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env->pc, env->spregs[TILEGX_SPR_CMPEXCH]);
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}
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TileGXCPU *cpu_tilegx_init(const char *cpu_model)
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{
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TileGXCPU *cpu;
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cpu = TILEGX_CPU(object_new(TYPE_TILEGX_CPU));
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object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
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return cpu;
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}
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static void tilegx_cpu_set_pc(CPUState *cs, vaddr value)
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{
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TileGXCPU *cpu = TILEGX_CPU(cs);
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cpu->env.pc = value;
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}
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static bool tilegx_cpu_has_work(CPUState *cs)
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{
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return true;
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}
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static void tilegx_cpu_reset(CPUState *s)
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{
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TileGXCPU *cpu = TILEGX_CPU(s);
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TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu);
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CPUTLGState *env = &cpu->env;
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tcc->parent_reset(s);
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memset(env, 0, sizeof(CPUTLGState));
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tlb_flush(s, 1);
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}
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static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev);
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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tcc->parent_realize(dev, errp);
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}
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static void tilegx_cpu_initfn(Object *obj)
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{
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CPUState *cs = CPU(obj);
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TileGXCPU *cpu = TILEGX_CPU(obj);
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CPUTLGState *env = &cpu->env;
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static bool tcg_initialized;
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cs->env_ptr = env;
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cpu_exec_init(cs, &error_abort);
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if (tcg_enabled() && !tcg_initialized) {
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tcg_initialized = true;
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tilegx_tcg_init();
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}
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}
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static void tilegx_cpu_do_interrupt(CPUState *cs)
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{
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cs->exception_index = -1;
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}
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static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
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int mmu_idx)
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{
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cpu_dump_state(cs, stderr, fprintf, 0);
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return 1;
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}
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static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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tilegx_cpu_do_interrupt(cs);
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return true;
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}
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return false;
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}
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static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc);
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tcc->parent_realize = dc->realize;
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dc->realize = tilegx_cpu_realizefn;
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tcc->parent_reset = cc->reset;
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cc->reset = tilegx_cpu_reset;
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cc->has_work = tilegx_cpu_has_work;
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cc->do_interrupt = tilegx_cpu_do_interrupt;
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cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
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cc->dump_state = tilegx_cpu_dump_state;
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cc->set_pc = tilegx_cpu_set_pc;
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cc->handle_mmu_fault = tilegx_cpu_handle_mmu_fault;
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cc->gdb_num_core_regs = 0;
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}
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static const TypeInfo tilegx_cpu_type_info = {
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.name = TYPE_TILEGX_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(TileGXCPU),
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.instance_init = tilegx_cpu_initfn,
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.class_size = sizeof(TileGXCPUClass),
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.class_init = tilegx_cpu_class_init,
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};
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static void tilegx_cpu_register_types(void)
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{
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type_register_static(&tilegx_cpu_type_info);
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}
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type_init(tilegx_cpu_register_types)
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175
target-tilegx/cpu.h
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175
target-tilegx/cpu.h
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/*
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* TILE-Gx virtual CPU header
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*
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* Copyright (c) 2015 Chen Gang
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CPU_TILEGX_H
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#define CPU_TILEGX_H
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#include "config.h"
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#include "qemu-common.h"
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#define TARGET_LONG_BITS 64
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#define CPUArchState struct CPUTLGState
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#include "exec/cpu-defs.h"
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/* TILE-Gx common register alias */
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#define TILEGX_R_RE 0 /* 0 register, for function/syscall return value */
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#define TILEGX_R_ERR 1 /* 1 register, for syscall errno flag */
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#define TILEGX_R_NR 10 /* 10 register, for syscall number */
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#define TILEGX_R_BP 52 /* 52 register, optional frame pointer */
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#define TILEGX_R_TP 53 /* TP register, thread local storage data */
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#define TILEGX_R_SP 54 /* SP register, stack pointer */
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#define TILEGX_R_LR 55 /* LR register, may save pc, but it is not pc */
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#define TILEGX_R_COUNT 56 /* Only 56 registers are really useful */
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#define TILEGX_R_SN 56 /* SN register, obsoleted, it likes zero register */
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#define TILEGX_R_IDN0 57 /* IDN0 register, cause IDN_ACCESS exception */
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#define TILEGX_R_IDN1 58 /* IDN1 register, cause IDN_ACCESS exception */
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#define TILEGX_R_UDN0 59 /* UDN0 register, cause UDN_ACCESS exception */
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#define TILEGX_R_UDN1 60 /* UDN1 register, cause UDN_ACCESS exception */
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#define TILEGX_R_UDN2 61 /* UDN2 register, cause UDN_ACCESS exception */
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#define TILEGX_R_UDN3 62 /* UDN3 register, cause UDN_ACCESS exception */
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#define TILEGX_R_ZERO 63 /* Zero register, always zero */
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#define TILEGX_R_NOREG 255 /* Invalid register value */
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/* TILE-Gx special registers used by outside */
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enum {
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TILEGX_SPR_CMPEXCH = 0,
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TILEGX_SPR_CRITICAL_SEC = 1,
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TILEGX_SPR_SIM_CONTROL = 2,
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TILEGX_SPR_COUNT
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};
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/* Exception numbers */
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typedef enum {
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TILEGX_EXCP_NONE = 0,
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TILEGX_EXCP_SYSCALL = 1,
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TILEGX_EXCP_OPCODE_UNKNOWN = 0x101,
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TILEGX_EXCP_OPCODE_UNIMPLEMENTED = 0x102,
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TILEGX_EXCP_OPCODE_CMPEXCH = 0x103,
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TILEGX_EXCP_OPCODE_CMPEXCH4 = 0x104,
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TILEGX_EXCP_OPCODE_EXCH = 0x105,
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TILEGX_EXCP_OPCODE_EXCH4 = 0x106,
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TILEGX_EXCP_OPCODE_FETCHADD = 0x107,
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TILEGX_EXCP_OPCODE_FETCHADD4 = 0x108,
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TILEGX_EXCP_OPCODE_FETCHADDGEZ = 0x109,
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TILEGX_EXCP_OPCODE_FETCHADDGEZ4 = 0x10a,
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TILEGX_EXCP_OPCODE_FETCHAND = 0x10b,
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TILEGX_EXCP_OPCODE_FETCHAND4 = 0x10c,
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TILEGX_EXCP_OPCODE_FETCHOR = 0x10d,
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TILEGX_EXCP_OPCODE_FETCHOR4 = 0x10e,
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TILEGX_EXCP_REG_IDN_ACCESS = 0x181,
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TILEGX_EXCP_REG_UDN_ACCESS = 0x182,
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TILEGX_EXCP_UNALIGNMENT = 0x201,
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TILEGX_EXCP_DBUG_BREAK = 0x301
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} TileExcp;
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typedef struct CPUTLGState {
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uint64_t regs[TILEGX_R_COUNT]; /* Common used registers by outside */
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uint64_t spregs[TILEGX_SPR_COUNT]; /* Special used registers by outside */
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uint64_t pc; /* Current pc */
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#if defined(CONFIG_USER_ONLY)
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uint32_t excparam; /* exception parameter */
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#endif
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CPU_COMMON
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} CPUTLGState;
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#include "qom/cpu.h"
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#define TYPE_TILEGX_CPU "tilegx-cpu"
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#define TILEGX_CPU_CLASS(klass) \
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OBJECT_CLASS_CHECK(TileGXCPUClass, (klass), TYPE_TILEGX_CPU)
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#define TILEGX_CPU(obj) \
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OBJECT_CHECK(TileGXCPU, (obj), TYPE_TILEGX_CPU)
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#define TILEGX_CPU_GET_CLASS(obj) \
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OBJECT_GET_CLASS(TileGXCPUClass, (obj), TYPE_TILEGX_CPU)
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/**
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* TileGXCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_reset: The parent class' reset handler.
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*
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* A Tile-Gx CPU model.
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*/
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typedef struct TileGXCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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void (*parent_reset)(CPUState *cpu);
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} TileGXCPUClass;
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/**
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* TileGXCPU:
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* @env: #CPUTLGState
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*
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* A Tile-GX CPU.
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*/
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typedef struct TileGXCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUTLGState env;
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} TileGXCPU;
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static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env)
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{
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return container_of(env, TileGXCPU, env);
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}
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#define ENV_GET_CPU(e) CPU(tilegx_env_get_cpu(e))
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#define ENV_OFFSET offsetof(TileGXCPU, env)
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/* TILE-Gx memory attributes */
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#define TARGET_PAGE_BITS 16 /* TILE-Gx uses 64KB page size */
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#define TARGET_PHYS_ADDR_SPACE_BITS 42
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#define TARGET_VIRT_ADDR_SPACE_BITS 64
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#define MMU_USER_IDX 0 /* Current memory operation is in user mode */
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#include "exec/cpu-all.h"
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void tilegx_tcg_init(void);
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int cpu_tilegx_exec(CPUState *s);
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int cpu_tilegx_signal_handler(int host_signum, void *pinfo, void *puc);
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TileGXCPU *cpu_tilegx_init(const char *cpu_model);
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#define cpu_init(cpu_model) CPU(cpu_tilegx_init(cpu_model))
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#define cpu_exec cpu_tilegx_exec
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#define cpu_gen_code cpu_tilegx_gen_code
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#define cpu_signal_handler cpu_tilegx_signal_handler
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static inline void cpu_get_tb_cpu_state(CPUTLGState *env, target_ulong *pc,
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target_ulong *cs_base, int *flags)
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{
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*pc = env->pc;
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*cs_base = 0;
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*flags = 0;
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}
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#include "exec/exec-all.h"
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#endif
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