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tcg-sparc: Support trunc_shr_i32

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Unlike a 64-bit shift op, allows the output to be in %l or %i registers
for sparcv8plus.

Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2014-03-05 12:27:23 -08:00
parent 9f44adc573
commit a24fba935a
2 changed files with 9 additions and 1 deletions
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8
tcg/sparc/tcg-target.c
View File

@ -1482,6 +1482,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_ext32u_i64: case INDEX_op_ext32u_i64:
tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRL); tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRL);
break; break;
case INDEX_op_trunc_shr_i32:
if (args[2] == 0) {
tcg_out_mov(s, TCG_TYPE_I32, args[0], args[1]);
} else {
tcg_out_arithi(s, args[0], args[1], args[2], SHIFT_SRLX);
}
break;
case INDEX_op_brcond_i64: case INDEX_op_brcond_i64:
tcg_out_brcond_i64(s, args[2], args[0], args[1], const_args[1], tcg_out_brcond_i64(s, args[2], args[0], args[1], const_args[1],
@ -1593,6 +1600,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
{ INDEX_op_ext32s_i64, { "r", "r" } }, { INDEX_op_ext32s_i64, { "r", "r" } },
{ INDEX_op_ext32u_i64, { "r", "r" } }, { INDEX_op_ext32u_i64, { "r", "r" } },
{ INDEX_op_trunc_shr_i32, { "r", "r" } },
{ INDEX_op_brcond_i64, { "rZ", "rJ" } }, { INDEX_op_brcond_i64, { "rZ", "rJ" } },
{ INDEX_op_setcond_i64, { "r", "rZ", "rJ" } }, { INDEX_op_setcond_i64, { "r", "rZ", "rJ" } },

2
tcg/sparc/tcg-target.h
View File

@ -117,7 +117,7 @@ typedef enum {
#define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0
#if TCG_TARGET_REG_BITS == 64 #if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_trunc_shr_i32 0 #define TCG_TARGET_HAS_trunc_shr_i32 1
#define TCG_TARGET_HAS_div_i64 1 #define TCG_TARGET_HAS_div_i64 1
#define TCG_TARGET_HAS_rem_i64 0 #define TCG_TARGET_HAS_rem_i64 0
#define TCG_TARGET_HAS_rot_i64 0 #define TCG_TARGET_HAS_rot_i64 0