Add limited support for the etrax ethernet controller.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4429 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
edgar_igl
parent
1ba13a5dfc
commit
a3ea5df588
453
hw/etraxfs_eth.c
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453
hw/etraxfs_eth.c
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@ -0,0 +1,453 @@
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/*
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* QEMU ETRAX Ethernet Controller.
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*
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* Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h>
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#include "hw.h"
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#include "net.h"
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#include "etraxfs_dma.h"
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#define D(x)
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#define R_STAT 0x2c
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#define RW_MGM_CTRL 0x28
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#define FS_ETH_MAX_REGS 0x5c
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struct qemu_phy
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{
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uint32_t regs[32];
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unsigned int (*read)(struct qemu_phy *phy, unsigned int req);
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void (*write)(struct qemu_phy *phy, unsigned int req, unsigned int data);
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};
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static unsigned int tdk_read(struct qemu_phy *phy, unsigned int req)
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{
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int regnum;
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unsigned r = 0;
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regnum = req & 0x1f;
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switch (regnum) {
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case 1:
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/* MR1. */
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/* Speeds and modes. */
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r |= (1 << 13) | (1 << 14);
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r |= (1 << 11) | (1 << 12);
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r |= (1 << 5); /* Autoneg complete. */
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r |= (1 << 3); /* Autoneg able. */
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r |= (1 << 2); /* Link. */
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break;
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default:
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r = phy->regs[regnum];
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break;
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}
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D(printf("%s %x = reg[%d]\n", __func__, r, regnum));
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return r;
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}
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static void
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tdk_write(struct qemu_phy *phy, unsigned int req, unsigned int data)
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{
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int regnum;
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regnum = req & 0x1f;
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D(printf("%s reg[%d] = %x\n", __func__, regnum, data));
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switch (regnum) {
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default:
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phy->regs[regnum] = data;
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break;
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}
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}
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static void
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tdk_init(struct qemu_phy *phy)
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{
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phy->read = tdk_read;
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phy->write = tdk_write;
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}
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struct qemu_mdio
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{
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/* bus. */
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int mdc;
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int mdio;
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/* decoder. */
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enum {
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PREAMBLE,
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SOF,
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OPC,
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ADDR,
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REQ,
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TURNAROUND,
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DATA
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} state;
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unsigned int drive;
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unsigned int cnt;
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unsigned int addr;
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unsigned int opc;
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unsigned int req;
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unsigned int data;
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struct qemu_phy *devs[32];
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};
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static void
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mdio_attach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr)
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{
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bus->devs[addr & 0x1f] = phy;
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}
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static void
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mdio_detach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr)
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{
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bus->devs[addr & 0x1f] = NULL;
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}
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static void mdio_read_req(struct qemu_mdio *bus)
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{
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struct qemu_phy *phy;
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phy = bus->devs[bus->addr];
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if (phy && phy->read)
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bus->data = phy->read(phy, bus->req);
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else
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bus->data = 0xffff;
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}
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static void mdio_write_req(struct qemu_mdio *bus)
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{
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struct qemu_phy *phy;
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phy = bus->devs[bus->addr];
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if (phy && phy->write)
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phy->write(phy, bus->req, bus->data);
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}
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static void mdio_cycle(struct qemu_mdio *bus)
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{
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bus->cnt++;
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D(printf("mdc=%d mdio=%d state=%d cnt=%d drv=%d\n",
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bus->mdc, bus->mdio, bus->state, bus->cnt, bus->drive));
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#if 0
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if (bus->mdc)
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printf("%d", bus->mdio);
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#endif
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switch (bus->state)
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{
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case PREAMBLE:
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if (bus->mdc) {
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if (bus->cnt >= (32 * 2) && !bus->mdio) {
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bus->cnt = 0;
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bus->state = SOF;
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bus->data = 0;
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}
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}
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break;
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case SOF:
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if (bus->mdc) {
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if (bus->mdio != 1)
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printf("WARNING: no SOF\n");
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if (bus->cnt == 1*2) {
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bus->cnt = 0;
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bus->opc = 0;
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bus->state = OPC;
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}
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}
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break;
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case OPC:
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if (bus->mdc) {
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bus->opc <<= 1;
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bus->opc |= bus->mdio & 1;
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if (bus->cnt == 2*2) {
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bus->cnt = 0;
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bus->addr = 0;
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bus->state = ADDR;
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}
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}
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break;
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case ADDR:
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if (bus->mdc) {
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bus->addr <<= 1;
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bus->addr |= bus->mdio & 1;
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if (bus->cnt == 5*2) {
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bus->cnt = 0;
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bus->req = 0;
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bus->state = REQ;
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}
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}
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break;
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case REQ:
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if (bus->mdc) {
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bus->req <<= 1;
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bus->req |= bus->mdio & 1;
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if (bus->cnt == 5*2) {
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bus->cnt = 0;
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bus->state = TURNAROUND;
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}
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}
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break;
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case TURNAROUND:
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if (bus->mdc && bus->cnt == 2*2) {
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bus->mdio = 0;
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bus->cnt = 0;
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if (bus->opc == 2) {
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bus->drive = 1;
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mdio_read_req(bus);
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bus->mdio = bus->data & 1;
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}
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bus->state = DATA;
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}
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break;
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case DATA:
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if (!bus->mdc) {
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if (bus->drive) {
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bus->mdio = bus->data & 1;
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bus->data >>= 1;
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}
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} else {
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if (!bus->drive) {
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bus->data <<= 1;
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bus->data |= bus->mdio;
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}
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if (bus->cnt == 16 * 2) {
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bus->cnt = 0;
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bus->state = PREAMBLE;
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mdio_write_req(bus);
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}
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}
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break;
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default:
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break;
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}
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}
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struct fs_eth
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{
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CPUState *env;
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qemu_irq *irq;
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target_phys_addr_t base;
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VLANClientState *vc;
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uint8_t macaddr[6];
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int ethregs;
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uint32_t regs[FS_ETH_MAX_REGS];
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unsigned char rx_fifo[1536];
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int rx_fifo_len;
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int rx_fifo_pos;
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struct etraxfs_dma_client *dma_out;
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struct etraxfs_dma_client *dma_in;
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/* MDIO bus. */
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struct qemu_mdio mdio_bus;
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/* PHY. */
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struct qemu_phy phy;
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};
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static uint32_t eth_rinvalid (void *opaque, target_phys_addr_t addr)
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{
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struct fs_eth *eth = opaque;
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CPUState *env = eth->env;
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cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
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addr, env->pc);
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return 0;
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}
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static uint32_t eth_readl (void *opaque, target_phys_addr_t addr)
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{
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struct fs_eth *eth = opaque;
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D(CPUState *env = eth->env);
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uint32_t r = 0;
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/* Make addr relative to this instances base. */
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addr -= eth->base;
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switch (addr) {
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case R_STAT:
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/* Attach an MDIO/PHY abstraction. */
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r = eth->mdio_bus.mdio & 1;
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break;
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default:
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r = eth->regs[addr];
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D(printf ("%s %x p=%x\n", __func__, addr, env->pc));
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break;
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}
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return r;
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}
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static void
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eth_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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struct fs_eth *eth = opaque;
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CPUState *env = eth->env;
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cpu_abort(env, "Unsupported short access. reg=%x pc=%x.\n",
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addr, env->pc);
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}
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static void
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eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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struct fs_eth *eth = opaque;
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CPUState *env = eth->env;
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/* Make addr relative to this instances base. */
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addr -= eth->base;
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switch (addr)
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{
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case RW_MGM_CTRL:
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/* Attach an MDIO/PHY abstraction. */
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if (value & 2)
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eth->mdio_bus.mdio = value & 1;
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if (eth->mdio_bus.mdc != (value & 4))
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mdio_cycle(ð->mdio_bus);
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eth->mdio_bus.mdc = !!(value & 4);
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break;
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default:
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printf ("%s %x %x pc=%x\n",
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__func__, addr, value, env->pc);
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break;
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}
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}
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static int eth_can_receive(void *opaque)
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{
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struct fs_eth *eth = opaque;
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int r;
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r = eth->rx_fifo_len == 0;
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if (!r) {
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/* TODO: signal fifo overrun. */
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printf("PACKET LOSS!\n");
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}
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return r;
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}
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static void eth_receive(void *opaque, const uint8_t *buf, int size)
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{
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struct fs_eth *eth = opaque;
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if (size > sizeof(eth->rx_fifo)) {
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/* TODO: signal error. */
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} else {
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memcpy(eth->rx_fifo, buf, size);
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/* +4, HW passes the CRC to sw. */
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eth->rx_fifo_len = size + 4;
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eth->rx_fifo_pos = 0;
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}
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}
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static void eth_rx_pull(void *opaque)
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{
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struct fs_eth *eth = opaque;
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int len;
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if (eth->rx_fifo_len) {
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D(printf("%s %d\n", __func__, eth->rx_fifo_len));
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#if 0
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{
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int i;
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for (i = 0; i < 32; i++)
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printf("%2.2x", eth->rx_fifo[i]);
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printf("\n");
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}
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#endif
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len = etraxfs_dmac_input(eth->dma_in,
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eth->rx_fifo + eth->rx_fifo_pos,
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eth->rx_fifo_len, 1);
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eth->rx_fifo_len -= len;
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eth->rx_fifo_pos += len;
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}
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}
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static int eth_tx_push(void *opaque, unsigned char *buf, int len)
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{
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struct fs_eth *eth = opaque;
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D(printf("%s buf=%p len=%d\n", __func__, buf, len));
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qemu_send_packet(eth->vc, buf, len);
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return len;
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}
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static CPUReadMemoryFunc *eth_read[] = {
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ð_rinvalid,
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ð_rinvalid,
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ð_readl,
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};
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static CPUWriteMemoryFunc *eth_write[] = {
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ð_winvalid,
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ð_winvalid,
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ð_writel,
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};
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void *etraxfs_eth_init(NICInfo *nd, CPUState *env,
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qemu_irq *irq, target_phys_addr_t base)
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{
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struct etraxfs_dma_client *dma = NULL;
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struct fs_eth *eth = NULL;
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dma = qemu_mallocz(sizeof *dma * 2);
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if (!dma)
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return NULL;
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eth = qemu_mallocz(sizeof *eth);
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if (!eth)
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goto err;
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dma[0].client.push = eth_tx_push;
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dma[0].client.opaque = eth;
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dma[1].client.opaque = eth;
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dma[1].client.pull = eth_rx_pull;
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eth->env = env;
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eth->base = base;
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eth->irq = irq;
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eth->dma_out = dma;
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eth->dma_in = dma + 1;
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memcpy(eth->macaddr, nd->macaddr, 6);
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/* Connect the phy. */
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tdk_init(ð->phy);
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mdio_attach(ð->mdio_bus, ð->phy, 0x1);
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eth->ethregs = cpu_register_io_memory(0, eth_read, eth_write, eth);
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cpu_register_physical_memory (base, 0x5c, eth->ethregs);
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eth->vc = qemu_new_vlan_client(nd->vlan,
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eth_receive, eth_can_receive, eth);
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return dma;
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err:
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qemu_free(eth);
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qemu_free(dma);
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return NULL;
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}
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