tcg: Implement insert_op_before
Rather reserving space in the op stream for optimization, let the optimizer add ops as necessary. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
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Richard Henderson
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0c627cdca2
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a4ce099a7a
@ -67,6 +67,37 @@ static void reset_temp(TCGArg temp)
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temps[temp].mask = -1;
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}
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static TCGOp *insert_op_before(TCGContext *s, TCGOp *old_op,
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TCGOpcode opc, int nargs)
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{
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int oi = s->gen_next_op_idx;
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int pi = s->gen_next_parm_idx;
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int prev = old_op->prev;
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int next = old_op - s->gen_op_buf;
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TCGOp *new_op;
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tcg_debug_assert(oi < OPC_BUF_SIZE);
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tcg_debug_assert(pi + nargs <= OPPARAM_BUF_SIZE);
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s->gen_next_op_idx = oi + 1;
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s->gen_next_parm_idx = pi + nargs;
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new_op = &s->gen_op_buf[oi];
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*new_op = (TCGOp){
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.opc = opc,
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.args = pi,
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.prev = prev,
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.next = next
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};
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if (prev >= 0) {
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s->gen_op_buf[prev].next = oi;
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} else {
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s->gen_first_op_idx = oi;
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}
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old_op->prev = oi;
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return new_op;
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}
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/* Reset all temporaries, given that there are NB_TEMPS of them. */
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static void reset_all_temps(int nb_temps)
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{
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@ -1108,8 +1139,8 @@ static void tcg_constant_folding(TCGContext *s)
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uint64_t a = ((uint64_t)ah << 32) | al;
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uint64_t b = ((uint64_t)bh << 32) | bl;
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TCGArg rl, rh;
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TCGOp *op2;
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TCGArg *args2;
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TCGOp *op2 = insert_op_before(s, op, INDEX_op_movi_i32, 2);
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TCGArg *args2 = &s->gen_opparam_buf[op2->args];
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if (opc == INDEX_op_add2_i32) {
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a += b;
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@ -1117,15 +1148,6 @@ static void tcg_constant_folding(TCGContext *s)
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a -= b;
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}
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/* We emit the extra nop when we emit the add2/sub2. */
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op2 = &s->gen_op_buf[oi_next];
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assert(op2->opc == INDEX_op_nop);
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/* But we still have to allocate args for the op. */
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op2->args = s->gen_next_parm_idx;
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s->gen_next_parm_idx += 2;
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args2 = &s->gen_opparam_buf[op2->args];
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rl = args[0];
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rh = args[1];
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tcg_opt_gen_movi(s, op, args, opc, rl, (uint32_t)a);
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@ -1144,17 +1166,8 @@ static void tcg_constant_folding(TCGContext *s)
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uint32_t b = temps[args[3]].val;
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uint64_t r = (uint64_t)a * b;
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TCGArg rl, rh;
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TCGOp *op2;
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TCGArg *args2;
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/* We emit the extra nop when we emit the mulu2. */
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op2 = &s->gen_op_buf[oi_next];
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assert(op2->opc == INDEX_op_nop);
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/* But we still have to allocate args for the op. */
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op2->args = s->gen_next_parm_idx;
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s->gen_next_parm_idx += 2;
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args2 = &s->gen_opparam_buf[op2->args];
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TCGOp *op2 = insert_op_before(s, op, INDEX_op_movi_i32, 2);
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TCGArg *args2 = &s->gen_opparam_buf[op2->args];
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rl = args[0];
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rh = args[1];
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21
tcg/tcg-op.c
21
tcg/tcg-op.c
@ -57,11 +57,6 @@ static void tcg_emit_op(TCGContext *ctx, TCGOpcode opc, int args)
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};
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}
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void tcg_gen_op0(TCGContext *ctx, TCGOpcode opc)
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{
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tcg_emit_op(ctx, opc, -1);
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}
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void tcg_gen_op1(TCGContext *ctx, TCGOpcode opc, TCGArg a1)
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{
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int pi = ctx->gen_next_parm_idx;
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@ -571,8 +566,6 @@ void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
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{
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if (TCG_TARGET_HAS_add2_i32) {
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tcg_gen_op6_i32(INDEX_op_add2_i32, rl, rh, al, ah, bl, bh);
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/* Allow the optimizer room to replace add2 with two moves. */
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tcg_gen_op0(&tcg_ctx, INDEX_op_nop);
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} else {
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TCGv_i64 t0 = tcg_temp_new_i64();
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TCGv_i64 t1 = tcg_temp_new_i64();
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@ -590,8 +583,6 @@ void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
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{
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if (TCG_TARGET_HAS_sub2_i32) {
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tcg_gen_op6_i32(INDEX_op_sub2_i32, rl, rh, al, ah, bl, bh);
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/* Allow the optimizer room to replace sub2 with two moves. */
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tcg_gen_op0(&tcg_ctx, INDEX_op_nop);
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} else {
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TCGv_i64 t0 = tcg_temp_new_i64();
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TCGv_i64 t1 = tcg_temp_new_i64();
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@ -608,8 +599,6 @@ void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2)
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{
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if (TCG_TARGET_HAS_mulu2_i32) {
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tcg_gen_op4_i32(INDEX_op_mulu2_i32, rl, rh, arg1, arg2);
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/* Allow the optimizer room to replace mulu2 with two moves. */
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tcg_gen_op0(&tcg_ctx, INDEX_op_nop);
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} else if (TCG_TARGET_HAS_muluh_i32) {
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TCGv_i32 t = tcg_temp_new_i32();
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tcg_gen_op3_i32(INDEX_op_mul_i32, t, arg1, arg2);
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@ -632,8 +621,6 @@ void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2)
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{
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if (TCG_TARGET_HAS_muls2_i32) {
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tcg_gen_op4_i32(INDEX_op_muls2_i32, rl, rh, arg1, arg2);
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/* Allow the optimizer room to replace muls2 with two moves. */
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tcg_gen_op0(&tcg_ctx, INDEX_op_nop);
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} else if (TCG_TARGET_HAS_mulsh_i32) {
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TCGv_i32 t = tcg_temp_new_i32();
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tcg_gen_op3_i32(INDEX_op_mul_i32, t, arg1, arg2);
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@ -1648,8 +1635,6 @@ void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
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{
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if (TCG_TARGET_HAS_add2_i64) {
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tcg_gen_op6_i64(INDEX_op_add2_i64, rl, rh, al, ah, bl, bh);
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/* Allow the optimizer room to replace add2 with two moves. */
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tcg_gen_op0(&tcg_ctx, INDEX_op_nop);
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} else {
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TCGv_i64 t0 = tcg_temp_new_i64();
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TCGv_i64 t1 = tcg_temp_new_i64();
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@ -1668,8 +1653,6 @@ void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
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{
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if (TCG_TARGET_HAS_sub2_i64) {
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tcg_gen_op6_i64(INDEX_op_sub2_i64, rl, rh, al, ah, bl, bh);
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/* Allow the optimizer room to replace sub2 with two moves. */
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tcg_gen_op0(&tcg_ctx, INDEX_op_nop);
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} else {
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TCGv_i64 t0 = tcg_temp_new_i64();
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TCGv_i64 t1 = tcg_temp_new_i64();
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@ -1687,8 +1670,6 @@ void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2)
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{
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if (TCG_TARGET_HAS_mulu2_i64) {
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tcg_gen_op4_i64(INDEX_op_mulu2_i64, rl, rh, arg1, arg2);
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/* Allow the optimizer room to replace mulu2 with two moves. */
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tcg_gen_op0(&tcg_ctx, INDEX_op_nop);
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} else if (TCG_TARGET_HAS_muluh_i64) {
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TCGv_i64 t = tcg_temp_new_i64();
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tcg_gen_op3_i64(INDEX_op_mul_i64, t, arg1, arg2);
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@ -1708,8 +1689,6 @@ void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2)
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{
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if (TCG_TARGET_HAS_muls2_i64) {
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tcg_gen_op4_i64(INDEX_op_muls2_i64, rl, rh, arg1, arg2);
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/* Allow the optimizer room to replace muls2 with two moves. */
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tcg_gen_op0(&tcg_ctx, INDEX_op_nop);
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} else if (TCG_TARGET_HAS_mulsh_i64) {
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TCGv_i64 t = tcg_temp_new_i64();
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tcg_gen_op3_i64(INDEX_op_mul_i64, t, arg1, arg2);
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@ -28,7 +28,6 @@
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/* Basic output routines. Not for general consumption. */
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void tcg_gen_op0(TCGContext *, TCGOpcode);
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void tcg_gen_op1(TCGContext *, TCGOpcode, TCGArg);
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void tcg_gen_op2(TCGContext *, TCGOpcode, TCGArg, TCGArg);
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void tcg_gen_op3(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg);
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