target-sparc: Implement ALIGNADDR* inline.
While ALIGNADDR was implemented out-of-line, ALIGNADDRL was not implemeneted at all. However, this is a very simple operation so we're better off doing this inline. Signed-off-by: Richard Henderson <rth@twiddle.net>
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				| @ -17,7 +17,6 @@ DEF_HELPER_2(wrccr, void, env, tl) | ||||
| DEF_HELPER_1(rdcwp, tl, env) | ||||
| DEF_HELPER_2(wrcwp, void, env, tl) | ||||
| DEF_HELPER_FLAGS_2(array8, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl) | ||||
| DEF_HELPER_3(alignaddr, tl, env, tl, tl) | ||||
| DEF_HELPER_1(popc, tl, tl) | ||||
| DEF_HELPER_3(ldda_asi, void, tl, int, int) | ||||
| DEF_HELPER_4(ldf_asi, void, tl, int, int, int) | ||||
|  | ||||
| @ -2324,6 +2324,20 @@ static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, | ||||
|     tcg_temp_free(t1); | ||||
|     tcg_temp_free(t2); | ||||
| } | ||||
| 
 | ||||
| static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left) | ||||
| { | ||||
|     TCGv tmp = tcg_temp_new(); | ||||
| 
 | ||||
|     tcg_gen_add_tl(tmp, s1, s2); | ||||
|     tcg_gen_andi_tl(dst, tmp, -8); | ||||
|     if (left) { | ||||
|         tcg_gen_neg_tl(tmp, tmp); | ||||
|     } | ||||
|     tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3); | ||||
| 
 | ||||
|     tcg_temp_free(tmp); | ||||
| } | ||||
| #endif | ||||
| 
 | ||||
| #define CHECK_IU_FEATURE(dc, FEATURE)                      \ | ||||
| @ -4167,11 +4181,17 @@ static void disas_sparc_insn(DisasContext * dc) | ||||
|                     CHECK_FPU_FEATURE(dc, VIS1); | ||||
|                     cpu_src1 = get_src1(insn, cpu_src1); | ||||
|                     gen_movl_reg_TN(rs2, cpu_src2); | ||||
|                     gen_helper_alignaddr(cpu_dst, cpu_env, cpu_src1, cpu_src2); | ||||
|                     gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0); | ||||
|                     gen_movl_TN_reg(rd, cpu_dst); | ||||
|                     break; | ||||
|                 case 0x01a: /* VIS I alignaddrl */ | ||||
|                     CHECK_FPU_FEATURE(dc, VIS1); | ||||
|                     cpu_src1 = get_src1(insn, cpu_src1); | ||||
|                     gen_movl_reg_TN(rs2, cpu_src2); | ||||
|                     gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1); | ||||
|                     gen_movl_TN_reg(rd, cpu_dst); | ||||
|                     break; | ||||
|                 case 0x019: /* VIS II bmask */ | ||||
|                 case 0x01a: /* VIS I alignaddrl */ | ||||
|                     // XXX
 | ||||
|                     goto illegal_insn; | ||||
|                 case 0x020: /* VIS I fcmple16 */ | ||||
|  | ||||
| @ -41,17 +41,6 @@ target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize) | ||||
|         GET_FIELD_SP(pixel_addr, 11, 12); | ||||
| } | ||||
| 
 | ||||
| target_ulong helper_alignaddr(CPUState *env, target_ulong addr, | ||||
|                               target_ulong offset) | ||||
| { | ||||
|     uint64_t tmp; | ||||
| 
 | ||||
|     tmp = addr + offset; | ||||
|     env->gsr &= ~7ULL; | ||||
|     env->gsr |= tmp & 7ULL; | ||||
|     return tmp & ~7ULL; | ||||
| } | ||||
| 
 | ||||
| uint64_t helper_faligndata(CPUState *env, uint64_t src1, uint64_t src2) | ||||
| { | ||||
|     uint64_t tmp; | ||||
|  | ||||
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