PPC: e500: change internal references away from mpc8544ds
No functional changes -- machine is still outwardly mpc8544ds. The references that are not changed contain mpc8544 hardware details that need to be parameterized if/when a different e500 platform wants to change them. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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				@ -1,5 +1,5 @@
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/*
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					/*
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 * QEMU PowerPC MPC8544DS board emulation
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					 * QEMU PowerPC e500-based platforms
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 *
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					 *
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 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
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					 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
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 *
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					 *
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@ -42,6 +42,7 @@
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#define RAM_SIZES_ALIGN            (64UL << 20)
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					#define RAM_SIZES_ALIGN            (64UL << 20)
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					/* TODO: parameterize */
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#define MPC8544_CCSRBAR_BASE       0xE0000000ULL
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					#define MPC8544_CCSRBAR_BASE       0xE0000000ULL
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#define MPC8544_CCSRBAR_SIZE       0x00100000ULL
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					#define MPC8544_CCSRBAR_SIZE       0x00100000ULL
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#define MPC8544_MPIC_REGS_BASE     (MPC8544_CCSRBAR_BASE + 0x40000ULL)
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					#define MPC8544_MPIC_REGS_BASE     (MPC8544_CCSRBAR_BASE + 0x40000ULL)
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@ -104,7 +105,7 @@ static void dt_serial_create(void *fdt, unsigned long long offset,
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    }
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					    }
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}
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					}
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static int mpc8544_load_device_tree(CPUPPCState *env,
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					static int ppce500_load_device_tree(CPUPPCState *env,
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                                    target_phys_addr_t addr,
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					                                    target_phys_addr_t addr,
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                                    target_phys_addr_t ramsize,
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					                                    target_phys_addr_t ramsize,
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                                    target_phys_addr_t initrd_base,
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					                                    target_phys_addr_t initrd_base,
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@ -388,7 +389,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env)
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    env->tlb_dirty = true;
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					    env->tlb_dirty = true;
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}
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					}
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static void mpc8544ds_cpu_reset_sec(void *opaque)
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					static void ppce500_cpu_reset_sec(void *opaque)
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{
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					{
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    PowerPCCPU *cpu = opaque;
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					    PowerPCCPU *cpu = opaque;
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    CPUPPCState *env = &cpu->env;
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					    CPUPPCState *env = &cpu->env;
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@ -401,7 +402,7 @@ static void mpc8544ds_cpu_reset_sec(void *opaque)
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    env->exception_index = EXCP_HLT;
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					    env->exception_index = EXCP_HLT;
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}
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					}
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static void mpc8544ds_cpu_reset(void *opaque)
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					static void ppce500_cpu_reset(void *opaque)
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{
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					{
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    PowerPCCPU *cpu = opaque;
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					    PowerPCCPU *cpu = opaque;
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    CPUPPCState *env = &cpu->env;
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					    CPUPPCState *env = &cpu->env;
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@ -417,7 +418,7 @@ static void mpc8544ds_cpu_reset(void *opaque)
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    mmubooke_create_initial_mapping(env);
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					    mmubooke_create_initial_mapping(env);
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}
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					}
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static void mpc8544ds_init(ram_addr_t ram_size,
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					static void ppce500_init(ram_addr_t ram_size,
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                         const char *boot_device,
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					                         const char *boot_device,
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                         const char *kernel_filename,
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					                         const char *kernel_filename,
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                         const char *kernel_cmdline,
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					                         const char *kernel_cmdline,
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@ -478,11 +479,11 @@ static void mpc8544ds_init(ram_addr_t ram_size,
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            /* Primary CPU */
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					            /* Primary CPU */
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            struct boot_info *boot_info;
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					            struct boot_info *boot_info;
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            boot_info = g_malloc0(sizeof(struct boot_info));
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					            boot_info = g_malloc0(sizeof(struct boot_info));
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            qemu_register_reset(mpc8544ds_cpu_reset, cpu);
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					            qemu_register_reset(ppce500_cpu_reset, cpu);
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            env->load_info = boot_info;
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					            env->load_info = boot_info;
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        } else {
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					        } else {
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            /* Secondary CPUs */
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					            /* Secondary CPUs */
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            qemu_register_reset(mpc8544ds_cpu_reset_sec, cpu);
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					            qemu_register_reset(ppce500_cpu_reset_sec, cpu);
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        }
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					        }
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    }
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					    }
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@ -577,7 +578,7 @@ static void mpc8544ds_init(ram_addr_t ram_size,
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        int dt_size;
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					        int dt_size;
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        dt_base = (loadaddr + kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
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					        dt_base = (loadaddr + kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
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        dt_size = mpc8544_load_device_tree(env, dt_base, ram_size, initrd_base,
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					        dt_size = ppce500_load_device_tree(env, dt_base, ram_size, initrd_base,
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                                           initrd_size, kernel_cmdline);
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					                                           initrd_size, kernel_cmdline);
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        if (dt_size < 0) {
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					        if (dt_size < 0) {
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            fprintf(stderr, "couldn't load device tree\n");
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					            fprintf(stderr, "couldn't load device tree\n");
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@ -595,16 +596,16 @@ static void mpc8544ds_init(ram_addr_t ram_size,
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    }
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					    }
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}
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					}
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static QEMUMachine mpc8544ds_machine = {
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					static QEMUMachine ppce500_machine = {
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    .name = "mpc8544ds",
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					    .name = "mpc8544ds",
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    .desc = "mpc8544ds",
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					    .desc = "mpc8544ds",
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    .init = mpc8544ds_init,
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					    .init = ppce500_init,
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    .max_cpus = 15,
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					    .max_cpus = 15,
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};
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					};
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static void mpc8544ds_machine_init(void)
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					static void ppce500_machine_init(void)
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{
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					{
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    qemu_register_machine(&mpc8544ds_machine);
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					    qemu_register_machine(&ppce500_machine);
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}
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					}
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machine_init(mpc8544ds_machine_init);
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					machine_init(ppce500_machine_init);
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