target-mips: redefine Integer Multiply and Divide instructions
Use "R6_" prefix in front of all new Multiply / Divide instructions for easier differentiation between R6 and preR6. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Leon Alrae
parent
bf7910c6b1
commit
b42ee5e1d9
16
disas/mips.c
16
disas/mips.c
@ -1217,6 +1217,22 @@ const struct mips_opcode mips_builtin_opcodes[] =
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them first. The assemblers uses a hash table based on the
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instruction name anyhow. */
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/* name, args, match, mask, pinfo, membership */
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{"mul", "d,s,t", 0x00000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
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{"muh", "d,s,t", 0x000000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
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{"mulu", "d,s,t", 0x00000099, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
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{"muhu", "d,s,t", 0x000000d9, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
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{"div", "d,s,t", 0x0000009a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
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{"mod", "d,s,t", 0x000000da, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
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{"divu", "d,s,t", 0x0000009b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
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{"modu", "d,s,t", 0x000000db, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
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{"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
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{"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
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{"dmulu", "d,s,t", 0x0000009d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
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{"dmuhu", "d,s,t", 0x000000dd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
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{"ddiv", "d,s,t", 0x0000009e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
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{"dmod", "d,s,t", 0x000000de, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
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{"ddivu", "d,s,t", 0x0000009f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
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{"dmodu", "d,s,t", 0x000000df, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
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{"ll", "t,o(b)", 0x7c000036, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6},
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{"sc", "t,o(b)", 0x7c000026, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6},
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{"lld", "t,o(b)", 0x7c000037, 0xfc00007f, LDD|RD_b|WR_t, 0, I64R6},
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@ -157,6 +157,7 @@ enum {
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OPC_DMULTU = 0x1D | OPC_SPECIAL,
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OPC_DDIV = 0x1E | OPC_SPECIAL,
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OPC_DDIVU = 0x1F | OPC_SPECIAL,
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/* 2 registers arithmetic / logic */
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OPC_ADD = 0x20 | OPC_SPECIAL,
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OPC_ADDU = 0x21 | OPC_SPECIAL,
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@ -212,6 +213,30 @@ enum {
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OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL,
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};
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/* R6 Multiply and Divide instructions have the same Opcode
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and function field as legacy OPC_MULT[U]/OPC_DIV[U] */
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#define MASK_R6_MULDIV(op) (MASK_SPECIAL(op) | (op & (0x7ff)))
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enum {
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R6_OPC_MUL = OPC_MULT | (2 << 6),
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R6_OPC_MUH = OPC_MULT | (3 << 6),
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R6_OPC_MULU = OPC_MULTU | (2 << 6),
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R6_OPC_MUHU = OPC_MULTU | (3 << 6),
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R6_OPC_DIV = OPC_DIV | (2 << 6),
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R6_OPC_MOD = OPC_DIV | (3 << 6),
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R6_OPC_DIVU = OPC_DIVU | (2 << 6),
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R6_OPC_MODU = OPC_DIVU | (3 << 6),
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R6_OPC_DMUL = OPC_DMULT | (2 << 6),
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R6_OPC_DMUH = OPC_DMULT | (3 << 6),
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R6_OPC_DMULU = OPC_DMULTU | (2 << 6),
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R6_OPC_DMUHU = OPC_DMULTU | (3 << 6),
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R6_OPC_DDIV = OPC_DDIV | (2 << 6),
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R6_OPC_DMOD = OPC_DDIV | (3 << 6),
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R6_OPC_DDIVU = OPC_DDIVU | (2 << 6),
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R6_OPC_DMODU = OPC_DDIVU | (3 << 6),
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};
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/* Multiplication variants of the vr54xx. */
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#define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
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@ -2691,6 +2716,238 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
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MIPS_DEBUG("%s %s", opn, regnames[reg]);
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}
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static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
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{
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const char *opn = "r6 mul/div";
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TCGv t0, t1;
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if (rd == 0) {
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/* Treat as NOP. */
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MIPS_DEBUG("NOP");
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return;
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}
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t0 = tcg_temp_new();
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t1 = tcg_temp_new();
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gen_load_gpr(t0, rs);
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gen_load_gpr(t1, rt);
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switch (opc) {
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case R6_OPC_DIV:
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{
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TCGv t2 = tcg_temp_new();
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TCGv t3 = tcg_temp_new();
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tcg_gen_ext32s_tl(t0, t0);
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tcg_gen_ext32s_tl(t1, t1);
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tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
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tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
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tcg_gen_and_tl(t2, t2, t3);
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tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
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tcg_gen_or_tl(t2, t2, t3);
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tcg_gen_movi_tl(t3, 0);
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tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
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tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
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tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
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tcg_temp_free(t3);
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tcg_temp_free(t2);
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}
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opn = "div";
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break;
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case R6_OPC_MOD:
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{
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TCGv t2 = tcg_temp_new();
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TCGv t3 = tcg_temp_new();
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tcg_gen_ext32s_tl(t0, t0);
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tcg_gen_ext32s_tl(t1, t1);
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tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
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tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
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tcg_gen_and_tl(t2, t2, t3);
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tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
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tcg_gen_or_tl(t2, t2, t3);
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tcg_gen_movi_tl(t3, 0);
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tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
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tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
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tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
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tcg_temp_free(t3);
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tcg_temp_free(t2);
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}
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opn = "mod";
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break;
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case R6_OPC_DIVU:
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{
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TCGv t2 = tcg_const_tl(0);
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TCGv t3 = tcg_const_tl(1);
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tcg_gen_ext32u_tl(t0, t0);
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tcg_gen_ext32u_tl(t1, t1);
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tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
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tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
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tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
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tcg_temp_free(t3);
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tcg_temp_free(t2);
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}
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opn = "divu";
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break;
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case R6_OPC_MODU:
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{
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TCGv t2 = tcg_const_tl(0);
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TCGv t3 = tcg_const_tl(1);
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tcg_gen_ext32u_tl(t0, t0);
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tcg_gen_ext32u_tl(t1, t1);
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tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
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tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
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tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
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tcg_temp_free(t3);
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tcg_temp_free(t2);
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}
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opn = "modu";
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break;
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case R6_OPC_MUL:
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{
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TCGv_i32 t2 = tcg_temp_new_i32();
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TCGv_i32 t3 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(t2, t0);
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tcg_gen_trunc_tl_i32(t3, t1);
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tcg_gen_mul_i32(t2, t2, t3);
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tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
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tcg_temp_free_i32(t2);
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tcg_temp_free_i32(t3);
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}
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opn = "mul";
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break;
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case R6_OPC_MUH:
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{
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TCGv_i32 t2 = tcg_temp_new_i32();
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TCGv_i32 t3 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(t2, t0);
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tcg_gen_trunc_tl_i32(t3, t1);
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tcg_gen_muls2_i32(t2, t3, t2, t3);
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tcg_gen_ext_i32_tl(cpu_gpr[rd], t3);
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tcg_temp_free_i32(t2);
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tcg_temp_free_i32(t3);
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}
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opn = "muh";
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break;
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case R6_OPC_MULU:
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{
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TCGv_i32 t2 = tcg_temp_new_i32();
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TCGv_i32 t3 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(t2, t0);
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tcg_gen_trunc_tl_i32(t3, t1);
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tcg_gen_mul_i32(t2, t2, t3);
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tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
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tcg_temp_free_i32(t2);
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tcg_temp_free_i32(t3);
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}
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opn = "mulu";
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break;
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case R6_OPC_MUHU:
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{
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TCGv_i32 t2 = tcg_temp_new_i32();
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TCGv_i32 t3 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(t2, t0);
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tcg_gen_trunc_tl_i32(t3, t1);
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tcg_gen_mulu2_i32(t2, t3, t2, t3);
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tcg_gen_ext_i32_tl(cpu_gpr[rd], t3);
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tcg_temp_free_i32(t2);
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tcg_temp_free_i32(t3);
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}
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opn = "muhu";
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break;
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#if defined(TARGET_MIPS64)
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case R6_OPC_DDIV:
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{
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TCGv t2 = tcg_temp_new();
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TCGv t3 = tcg_temp_new();
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tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63);
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tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL);
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tcg_gen_and_tl(t2, t2, t3);
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tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
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tcg_gen_or_tl(t2, t2, t3);
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tcg_gen_movi_tl(t3, 0);
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tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
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tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
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tcg_temp_free(t3);
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tcg_temp_free(t2);
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}
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opn = "ddiv";
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break;
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case R6_OPC_DMOD:
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{
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TCGv t2 = tcg_temp_new();
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TCGv t3 = tcg_temp_new();
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tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63);
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tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL);
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tcg_gen_and_tl(t2, t2, t3);
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tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
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tcg_gen_or_tl(t2, t2, t3);
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tcg_gen_movi_tl(t3, 0);
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tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
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tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
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tcg_temp_free(t3);
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tcg_temp_free(t2);
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}
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opn = "dmod";
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break;
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case R6_OPC_DDIVU:
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{
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TCGv t2 = tcg_const_tl(0);
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TCGv t3 = tcg_const_tl(1);
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tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
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tcg_gen_divu_i64(cpu_gpr[rd], t0, t1);
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tcg_temp_free(t3);
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tcg_temp_free(t2);
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}
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opn = "ddivu";
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break;
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case R6_OPC_DMODU:
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{
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TCGv t2 = tcg_const_tl(0);
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TCGv t3 = tcg_const_tl(1);
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tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
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tcg_gen_remu_i64(cpu_gpr[rd], t0, t1);
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tcg_temp_free(t3);
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tcg_temp_free(t2);
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}
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opn = "dmodu";
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break;
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case R6_OPC_DMUL:
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tcg_gen_mul_i64(cpu_gpr[rd], t0, t1);
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opn = "dmul";
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break;
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case R6_OPC_DMUH:
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{
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TCGv t2 = tcg_temp_new();
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tcg_gen_muls2_i64(t2, cpu_gpr[rd], t0, t1);
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tcg_temp_free(t2);
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}
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opn = "dmuh";
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break;
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case R6_OPC_DMULU:
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tcg_gen_mul_i64(cpu_gpr[rd], t0, t1);
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opn = "dmulu";
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break;
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case R6_OPC_DMUHU:
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{
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TCGv t2 = tcg_temp_new();
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tcg_gen_mulu2_i64(t2, cpu_gpr[rd], t0, t1);
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tcg_temp_free(t2);
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}
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opn = "dmuhu";
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break;
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#endif
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default:
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MIPS_INVAL(opn);
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generate_exception(ctx, EXCP_RI);
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goto out;
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}
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(void)opn; /* avoid a compiler warning */
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MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]);
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out:
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tcg_temp_free(t0);
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tcg_temp_free(t1);
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}
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static void gen_muldiv(DisasContext *ctx, uint32_t opc,
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int acc, int rs, int rt)
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{
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@ -14491,7 +14748,7 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
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static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
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{
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int rs, rt, rd;
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uint32_t op1;
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uint32_t op1, op2;
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rs = (ctx->opcode >> 21) & 0x1f;
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rt = (ctx->opcode >> 16) & 0x1f;
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@ -14499,10 +14756,51 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
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op1 = MASK_SPECIAL(ctx->opcode);
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switch (op1) {
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case OPC_MULT ... OPC_DIVU:
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op2 = MASK_R6_MULDIV(ctx->opcode);
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switch (op2) {
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case R6_OPC_MUL:
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case R6_OPC_MUH:
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case R6_OPC_MULU:
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case R6_OPC_MUHU:
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case R6_OPC_DIV:
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case R6_OPC_MOD:
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case R6_OPC_DIVU:
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case R6_OPC_MODU:
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gen_r6_muldiv(ctx, op2, rd, rs, rt);
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break;
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default:
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MIPS_INVAL("special_r6 muldiv");
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generate_exception(ctx, EXCP_RI);
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break;
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}
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break;
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case OPC_SELEQZ:
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case OPC_SELNEZ:
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gen_cond_move(ctx, op1, rd, rs, rt);
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break;
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#if defined(TARGET_MIPS64)
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case OPC_DMULT ... OPC_DDIVU:
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op2 = MASK_R6_MULDIV(ctx->opcode);
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switch (op2) {
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case R6_OPC_DMUL:
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case R6_OPC_DMUH:
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case R6_OPC_DMULU:
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case R6_OPC_DMUHU:
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case R6_OPC_DDIV:
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case R6_OPC_DMOD:
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case R6_OPC_DDIVU:
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case R6_OPC_DMODU:
|
||||
check_mips_64(ctx);
|
||||
gen_r6_muldiv(ctx, op2, rd, rs, rt);
|
||||
break;
|
||||
default:
|
||||
MIPS_INVAL("special_r6 muldiv");
|
||||
generate_exception(ctx, EXCP_RI);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
default: /* Invalid */
|
||||
MIPS_INVAL("special_r6");
|
||||
generate_exception(ctx, EXCP_RI);
|
||||
@ -14512,12 +14810,13 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
|
||||
|
||||
static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
|
||||
{
|
||||
int rs, rt, rd;
|
||||
int rs, rt, rd, sa;
|
||||
uint32_t op1;
|
||||
|
||||
rs = (ctx->opcode >> 21) & 0x1f;
|
||||
rt = (ctx->opcode >> 16) & 0x1f;
|
||||
rd = (ctx->opcode >> 11) & 0x1f;
|
||||
sa = (ctx->opcode >> 6) & 0x1f;
|
||||
|
||||
op1 = MASK_SPECIAL(ctx->opcode);
|
||||
switch (op1) {
|
||||
@ -14545,6 +14844,27 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
|
||||
generate_exception_err(ctx, EXCP_CpU, 1);
|
||||
}
|
||||
break;
|
||||
case OPC_MULT:
|
||||
case OPC_MULTU:
|
||||
if (sa) {
|
||||
check_insn(ctx, INSN_VR54XX);
|
||||
op1 = MASK_MUL_VR54XX(ctx->opcode);
|
||||
gen_mul_vr54xx(ctx, op1, rd, rs, rt);
|
||||
} else {
|
||||
gen_muldiv(ctx, op1, rd & 3, rs, rt);
|
||||
}
|
||||
break;
|
||||
case OPC_DIV:
|
||||
case OPC_DIVU:
|
||||
gen_muldiv(ctx, op1, 0, rs, rt);
|
||||
break;
|
||||
#if defined(TARGET_MIPS64)
|
||||
case OPC_DMULT ... OPC_DDIVU:
|
||||
check_insn(ctx, ISA_MIPS3);
|
||||
check_mips_64(ctx);
|
||||
gen_muldiv(ctx, op1, 0, rs, rt);
|
||||
break;
|
||||
#endif
|
||||
default: /* Invalid */
|
||||
MIPS_INVAL("special_legacy");
|
||||
generate_exception(ctx, EXCP_RI);
|
||||
@ -14617,20 +14937,6 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
|
||||
case OPC_XOR:
|
||||
gen_logic(ctx, op1, rd, rs, rt);
|
||||
break;
|
||||
case OPC_MULT:
|
||||
case OPC_MULTU:
|
||||
if (sa) {
|
||||
check_insn(ctx, INSN_VR54XX);
|
||||
op1 = MASK_MUL_VR54XX(ctx->opcode);
|
||||
gen_mul_vr54xx(ctx, op1, rd, rs, rt);
|
||||
} else {
|
||||
gen_muldiv(ctx, op1, rd & 3, rs, rt);
|
||||
}
|
||||
break;
|
||||
case OPC_DIV:
|
||||
case OPC_DIVU:
|
||||
gen_muldiv(ctx, op1, 0, rs, rt);
|
||||
break;
|
||||
case OPC_JR ... OPC_JALR:
|
||||
gen_compute_branch(ctx, op1, 4, rs, rd, sa);
|
||||
break;
|
||||
@ -14742,11 +15048,6 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case OPC_DMULT ... OPC_DDIVU:
|
||||
check_insn(ctx, ISA_MIPS3);
|
||||
check_mips_64(ctx);
|
||||
gen_muldiv(ctx, op1, 0, rs, rt);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
if (ctx->insn_flags & ISA_MIPS32R6) {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user