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tcg/ia64: implement movcond_i32/64

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Implement movcond_i32/64 on ia64 hosts. It is not possible to have
immediate compare arguments without adding a new bundle, but it is
possible to have 22-bit immediate value arguments.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2012-10-09 21:53:55 +02:00
parent da897bf5ae
commit b90cf71692
2 changed files with 40 additions and 2 deletions
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38
tcg/ia64/tcg-target.c
View File

@ -1404,6 +1404,34 @@ static inline void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg ret,
tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, 0, TCG_REG_R0)); tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, 0, TCG_REG_R0));
} }
static inline void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGArg ret,
TCGArg c1, TCGArg c2,
TCGArg v1, int const_v1,
TCGArg v2, int const_v2, int cmp4)
{
uint64_t opc1, opc2;
if (const_v1) {
opc1 = tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, v1, TCG_REG_R0);
} else if (ret == v1) {
opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
} else {
opc1 = tcg_opc_a4(TCG_REG_P6, OPC_ADDS_A4, ret, 0, v1);
}
if (const_v2) {
opc2 = tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, v2, TCG_REG_R0);
} else if (ret == v2) {
opc2 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
} else {
opc2 = tcg_opc_a4(TCG_REG_P7, OPC_ADDS_A4, ret, 0, v2);
}
tcg_out_bundle(s, MmI,
tcg_opc_cmp_a(TCG_REG_P0, cond, c1, c2, cmp4),
opc1,
opc2);
}
#if defined(CONFIG_SOFTMMU) #if defined(CONFIG_SOFTMMU)
#include "../../softmmu_defs.h" #include "../../softmmu_defs.h"
@ -2106,6 +2134,14 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_setcond_i64: case INDEX_op_setcond_i64:
tcg_out_setcond(s, args[3], args[0], args[1], args[2], 0); tcg_out_setcond(s, args[3], args[0], args[1], args[2], 0);
break; break;
case INDEX_op_movcond_i32:
tcg_out_movcond(s, args[5], args[0], args[1], args[2],
args[3], const_args[3], args[4], const_args[4], 1);
break;
case INDEX_op_movcond_i64:
tcg_out_movcond(s, args[5], args[0], args[1], args[2],
args[3], const_args[3], args[4], const_args[4], 0);
break;
case INDEX_op_qemu_ld8u: case INDEX_op_qemu_ld8u:
tcg_out_qemu_ld(s, args, 0); tcg_out_qemu_ld(s, args, 0);
@ -2196,6 +2232,7 @@ static const TCGTargetOpDef ia64_op_defs[] = {
{ INDEX_op_brcond_i32, { "rI", "rI" } }, { INDEX_op_brcond_i32, { "rI", "rI" } },
{ INDEX_op_setcond_i32, { "r", "rZ", "rZ" } }, { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
{ INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rI", "rI" } },
{ INDEX_op_mov_i64, { "r", "r" } }, { INDEX_op_mov_i64, { "r", "r" } },
{ INDEX_op_movi_i64, { "r" } }, { INDEX_op_movi_i64, { "r" } },
@ -2245,6 +2282,7 @@ static const TCGTargetOpDef ia64_op_defs[] = {
{ INDEX_op_brcond_i64, { "rI", "rI" } }, { INDEX_op_brcond_i64, { "rI", "rI" } },
{ INDEX_op_setcond_i64, { "r", "rZ", "rZ" } }, { INDEX_op_setcond_i64, { "r", "rZ", "rZ" } },
{ INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rI", "rI" } },
{ INDEX_op_qemu_ld8u, { "r", "r" } }, { INDEX_op_qemu_ld8u, { "r", "r" } },
{ INDEX_op_qemu_ld8s, { "r", "r" } }, { INDEX_op_qemu_ld8s, { "r", "r" } },

4
tcg/ia64/tcg-target.h
View File

@ -131,10 +131,10 @@ typedef enum {
#define TCG_TARGET_HAS_orc_i64 1 #define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_rot_i32 1 #define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_deposit_i32 0 #define TCG_TARGET_HAS_deposit_i32 0
#define TCG_TARGET_HAS_deposit_i64 0 #define TCG_TARGET_HAS_deposit_i64 0
#define TCG_TARGET_HAS_movcond_i32 0
#define TCG_TARGET_HAS_movcond_i64 0
/* optional instructions automatically implemented */ /* optional instructions automatically implemented */
#define TCG_TARGET_HAS_neg_i32 0 /* sub r1, r0, r3 */ #define TCG_TARGET_HAS_neg_i32 0 /* sub r1, r0, r3 */