Sparc: fix coding style
Before the next patch, fix coding style of the areas affected. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Blue Swirl
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b1f88301b5
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c65f6fd4bc
@ -1144,7 +1144,7 @@ void cpu_reset(CPUSPARCState *env)
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env->cleanwin = env->nwindows - 2;
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env->cansave = env->nwindows - 2;
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env->pstate = PS_RMO | PS_PEF | PS_IE;
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env->asi = 0x82; // Primary no-fault
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env->asi = 0x82; /* Primary no-fault */
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#endif
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#else
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#if !defined(TARGET_SPARC64)
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@ -1172,14 +1172,16 @@ static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
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{
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sparc_def_t def1, *def = &def1;
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if (cpu_sparc_find_by_name(def, cpu_model) < 0)
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if (cpu_sparc_find_by_name(def, cpu_model) < 0) {
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return -1;
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}
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env->def = g_malloc0(sizeof(*def));
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memcpy(env->def, def, sizeof(*def));
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#if defined(CONFIG_USER_ONLY)
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if ((env->def->features & CPU_FEATURE_FLOAT))
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if ((env->def->features & CPU_FEATURE_FLOAT)) {
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env->def->features |= CPU_FEATURE_FLOAT128;
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}
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#endif
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env->cpu_model_str = cpu_model;
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env->version = def->iu_version;
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@ -1359,7 +1361,7 @@ static const sparc_def_t sparc_defs[] = {
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},
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{
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.name = "Sun UltraSparc T1",
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// defined in sparc_ifu_fdp.v and ctu.h
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/* defined in sparc_ifu_fdp.v and ctu.h */
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.iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_sun4v,
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@ -1370,7 +1372,7 @@ static const sparc_def_t sparc_defs[] = {
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},
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{
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.name = "Sun UltraSparc T2",
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// defined in tlu_asi_ctl.v and n2_revid_cust.v
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/* defined in tlu_asi_ctl.v and n2_revid_cust.v */
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.iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_sun4v,
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@ -1512,10 +1514,10 @@ static const sparc_def_t sparc_defs[] = {
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI SuperSparc 40", // STP1020NPGA
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.iu_version = 0x41000000, // SuperSPARC 2.x
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.name = "TI SuperSparc 40", /* STP1020NPGA */
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.iu_version = 0x41000000, /* SuperSPARC 2.x */
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.fpu_version = 0 << 17,
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.mmu_version = 0x00000800, // SuperSPARC 2.x, no MXCC
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.mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x0000ffff,
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@ -1525,10 +1527,10 @@ static const sparc_def_t sparc_defs[] = {
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI SuperSparc 50", // STP1020PGA
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.iu_version = 0x40000000, // SuperSPARC 3.x
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.name = "TI SuperSparc 50", /* STP1020PGA */
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.iu_version = 0x40000000, /* SuperSPARC 3.x */
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.fpu_version = 0 << 17,
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.mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC
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.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x0000ffff,
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@ -1539,9 +1541,9 @@ static const sparc_def_t sparc_defs[] = {
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},
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{
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.name = "TI SuperSparc 51",
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.iu_version = 0x40000000, // SuperSPARC 3.x
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.iu_version = 0x40000000, /* SuperSPARC 3.x */
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.fpu_version = 0 << 17,
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.mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC
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.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x0000ffff,
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@ -1552,10 +1554,10 @@ static const sparc_def_t sparc_defs[] = {
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI SuperSparc 60", // STP1020APGA
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.iu_version = 0x40000000, // SuperSPARC 3.x
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.name = "TI SuperSparc 60", /* STP1020APGA */
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.iu_version = 0x40000000, /* SuperSPARC 3.x */
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.fpu_version = 0 << 17,
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.mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC
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.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x0000ffff,
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@ -1566,9 +1568,9 @@ static const sparc_def_t sparc_defs[] = {
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},
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{
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.name = "TI SuperSparc 61",
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.iu_version = 0x44000000, // SuperSPARC 3.x
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.iu_version = 0x44000000, /* SuperSPARC 3.x */
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.fpu_version = 0 << 17,
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.mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC
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.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x0000ffff,
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@ -1580,9 +1582,9 @@ static const sparc_def_t sparc_defs[] = {
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},
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{
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.name = "TI SuperSparc II",
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.iu_version = 0x40000000, // SuperSPARC II 1.x
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.iu_version = 0x40000000, /* SuperSPARC II 1.x */
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.fpu_version = 0 << 17,
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.mmu_version = 0x08000000, // SuperSPARC II 1.x, MXCC
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.mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x0000ffff,
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@ -1711,23 +1713,26 @@ static void print_features(FILE *f, fprintf_function cpu_fprintf,
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{
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(feature_name); i++)
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for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
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if (feature_name[i] && (features & (1 << i))) {
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if (prefix)
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if (prefix) {
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(*cpu_fprintf)(f, "%s", prefix);
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}
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(*cpu_fprintf)(f, "%s ", feature_name[i]);
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}
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}
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}
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static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
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{
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(feature_name); i++)
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for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
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if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
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*features |= 1 << i;
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return;
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}
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}
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fprintf(stderr, "CPU feature %s not found\n", flagname);
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}
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@ -1747,8 +1752,9 @@ static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model)
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def = &sparc_defs[i];
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}
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}
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if (!def)
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if (!def) {
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goto error;
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}
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memcpy(cpu_def, def, sizeof(*def));
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featurestr = strtok(NULL, ",");
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@ -1839,7 +1845,8 @@ void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
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(*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x NWINS %d ",
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(*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx
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" FPU %08x MMU %08x NWINS %d ",
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sparc_defs[i].name,
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sparc_defs[i].iu_version,
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sparc_defs[i].fpu_version,
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@ -1864,9 +1871,9 @@ void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
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static void cpu_print_cc(FILE *f, fprintf_function cpu_fprintf,
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uint32_t cc)
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{
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cpu_fprintf(f, "%c%c%c%c", cc & PSR_NEG? 'N' : '-',
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cc & PSR_ZERO? 'Z' : '-', cc & PSR_OVF? 'V' : '-',
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cc & PSR_CARRY? 'C' : '-');
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cpu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-',
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cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-',
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cc & PSR_CARRY ? 'C' : '-');
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}
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#ifdef TARGET_SPARC64
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@ -1909,11 +1916,13 @@ void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
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}
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cpu_fprintf(f, "\nFloating Point Registers:\n");
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for (i = 0; i < TARGET_FPREGS; i++) {
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if ((i & 3) == 0)
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if ((i & 3) == 0) {
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cpu_fprintf(f, "%%f%02d:", i);
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}
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cpu_fprintf(f, " %016f", *(float *)&env->fpr[i]);
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if ((i & 3) == 3)
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if ((i & 3) == 3) {
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cpu_fprintf(f, "\n");
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}
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}
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#ifdef TARGET_SPARC64
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cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
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@ -1932,8 +1941,8 @@ void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
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#else
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cpu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env));
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cpu_print_cc(f, cpu_fprintf, cpu_get_psr(env));
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cpu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs? 'S' : '-',
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env->psrps? 'P' : '-', env->psret? 'E' : '-',
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cpu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-',
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env->psrps ? 'P' : '-', env->psret ? 'E' : '-',
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env->wim);
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cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n",
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env->fsr, env->y);
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