target-arm: Add AArch64 access to PAR_EL1
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1441311266-8644-4-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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				@ -2993,6 +2993,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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    { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
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					    { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
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      .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
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					      .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
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      .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
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					      .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
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					    { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
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					      .type = ARM_CP_ALIAS,
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					      .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
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					      .access = PL1_RW, .resetvalue = 0,
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					      .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
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					      .writefn = par_write },
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#endif
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					#endif
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    /* TLB invalidate last level of translation table walk */
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					    /* TLB invalidate last level of translation table walk */
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    { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
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					    { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
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