david.venhoff/QEMU-Nyx-fork
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

target-mips: remove wrong checks for recip.fmt and rsqrt.fmt

Browse Source 
Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
they require any particular mode for its FPU. This patch removes the checks
that may break a program that uses these instructions.

Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Petar Jovanovic 2015-08-26 14:12:20 +02:00 committed by Leon Alrae
parent 71f303cd24
commit ca6c7803d2
1 changed files with 2 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
target-mips/translate.c
View File

@ -9290,7 +9290,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "movn.s"; opn = "movn.s";
break; break;
case OPC_RECIP_S: case OPC_RECIP_S:
check_cop1x(ctx);
{ {
TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp0 = tcg_temp_new_i32();
@ -9302,7 +9301,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "recip.s"; opn = "recip.s";
break; break;
case OPC_RSQRT_S: case OPC_RSQRT_S:
check_cop1x(ctx);
{ {
TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp0 = tcg_temp_new_i32();
@ -9835,7 +9833,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "movn.d"; opn = "movn.d";
break; break;
case OPC_RECIP_D: case OPC_RECIP_D:
check_cp1_64bitmode(ctx); check_cp1_registers(ctx, fs | fd);
{ {
TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp0 = tcg_temp_new_i64();
@ -9847,7 +9845,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "recip.d"; opn = "recip.d";
break; break;
case OPC_RSQRT_D: case OPC_RSQRT_D:
check_cp1_64bitmode(ctx); check_cp1_registers(ctx, fs | fd);
{ {
TCGv_i64 fp0 = tcg_temp_new_i64(); TCGv_i64 fp0 = tcg_temp_new_i64();