fpu/softfloat: re-factor muladd
We can now add float16_muladd and use the common decompose and canonicalize functions to have a single implementation for float16/32/64 muladd functions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alex Bennée
parent
cf07323d49
commit
d446830a3a
@ -729,58 +729,6 @@ static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status)
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}
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}
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}
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}
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/*----------------------------------------------------------------------------
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| Takes three single-precision floating-point values `a', `b' and `c', one of
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| which is a NaN, and returns the appropriate NaN result. If any of `a',
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| `b' or `c' is a signaling NaN, the invalid exception is raised.
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| The input infzero indicates whether a*b was 0*inf or inf*0 (in which case
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| obviously c is a NaN, and whether to propagate c or some other NaN is
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| implementation defined).
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*----------------------------------------------------------------------------*/
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static float32 propagateFloat32MulAddNaN(float32 a, float32 b,
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float32 c, flag infzero,
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float_status *status)
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{
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flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
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cIsQuietNaN, cIsSignalingNaN;
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int which;
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aIsQuietNaN = float32_is_quiet_nan(a, status);
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aIsSignalingNaN = float32_is_signaling_nan(a, status);
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bIsQuietNaN = float32_is_quiet_nan(b, status);
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bIsSignalingNaN = float32_is_signaling_nan(b, status);
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cIsQuietNaN = float32_is_quiet_nan(c, status);
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cIsSignalingNaN = float32_is_signaling_nan(c, status);
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if (aIsSignalingNaN | bIsSignalingNaN | cIsSignalingNaN) {
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float_raise(float_flag_invalid, status);
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}
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which = pickNaNMulAdd(aIsQuietNaN, aIsSignalingNaN,
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bIsQuietNaN, bIsSignalingNaN,
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cIsQuietNaN, cIsSignalingNaN, infzero, status);
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if (status->default_nan_mode) {
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/* Note that this check is after pickNaNMulAdd so that function
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* has an opportunity to set the Invalid flag.
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*/
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return float32_default_nan(status);
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}
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switch (which) {
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case 0:
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return float32_maybe_silence_nan(a, status);
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case 1:
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return float32_maybe_silence_nan(b, status);
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case 2:
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return float32_maybe_silence_nan(c, status);
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case 3:
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default:
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return float32_default_nan(status);
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}
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}
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#ifdef NO_SIGNALING_NANS
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#ifdef NO_SIGNALING_NANS
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int float64_is_quiet_nan(float64 a_, float_status *status)
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int float64_is_quiet_nan(float64 a_, float_status *status)
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{
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{
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@ -936,58 +884,6 @@ static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status)
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}
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}
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}
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}
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/*----------------------------------------------------------------------------
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| Takes three double-precision floating-point values `a', `b' and `c', one of
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| which is a NaN, and returns the appropriate NaN result. If any of `a',
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| `b' or `c' is a signaling NaN, the invalid exception is raised.
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| The input infzero indicates whether a*b was 0*inf or inf*0 (in which case
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| obviously c is a NaN, and whether to propagate c or some other NaN is
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| implementation defined).
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*----------------------------------------------------------------------------*/
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static float64 propagateFloat64MulAddNaN(float64 a, float64 b,
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float64 c, flag infzero,
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float_status *status)
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{
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flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
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cIsQuietNaN, cIsSignalingNaN;
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int which;
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aIsQuietNaN = float64_is_quiet_nan(a, status);
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aIsSignalingNaN = float64_is_signaling_nan(a, status);
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bIsQuietNaN = float64_is_quiet_nan(b, status);
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bIsSignalingNaN = float64_is_signaling_nan(b, status);
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cIsQuietNaN = float64_is_quiet_nan(c, status);
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cIsSignalingNaN = float64_is_signaling_nan(c, status);
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if (aIsSignalingNaN | bIsSignalingNaN | cIsSignalingNaN) {
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float_raise(float_flag_invalid, status);
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}
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which = pickNaNMulAdd(aIsQuietNaN, aIsSignalingNaN,
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bIsQuietNaN, bIsSignalingNaN,
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cIsQuietNaN, cIsSignalingNaN, infzero, status);
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if (status->default_nan_mode) {
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/* Note that this check is after pickNaNMulAdd so that function
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* has an opportunity to set the Invalid flag.
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*/
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return float64_default_nan(status);
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}
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switch (which) {
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case 0:
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return float64_maybe_silence_nan(a, status);
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case 1:
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return float64_maybe_silence_nan(b, status);
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case 2:
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return float64_maybe_silence_nan(c, status);
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case 3:
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default:
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return float64_default_nan(status);
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}
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}
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#ifdef NO_SIGNALING_NANS
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#ifdef NO_SIGNALING_NANS
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int floatx80_is_quiet_nan(floatx80 a_, float_status *status)
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int floatx80_is_quiet_nan(floatx80 a_, float_status *status)
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{
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{
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742
fpu/softfloat.c
742
fpu/softfloat.c
@ -580,6 +580,40 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s)
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return a;
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return a;
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}
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}
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static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c,
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bool inf_zero, float_status *s)
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{
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if (is_snan(a.cls) || is_snan(b.cls) || is_snan(c.cls)) {
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s->float_exception_flags |= float_flag_invalid;
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}
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if (s->default_nan_mode) {
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a.cls = float_class_dnan;
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} else {
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switch (pickNaNMulAdd(is_qnan(a.cls), is_snan(a.cls),
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is_qnan(b.cls), is_snan(b.cls),
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is_qnan(c.cls), is_snan(c.cls),
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inf_zero, s)) {
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case 0:
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break;
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case 1:
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a = b;
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break;
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case 2:
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a = c;
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break;
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case 3:
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a.cls = float_class_dnan;
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return a;
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default:
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g_assert_not_reached();
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}
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a.cls = float_class_msnan;
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}
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return a;
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}
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/*
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/*
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* Returns the result of adding or subtracting the values of the
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* Returns the result of adding or subtracting the values of the
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* floating-point values `a' and `b'. The operation is performed
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* floating-point values `a' and `b'. The operation is performed
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@ -816,6 +850,243 @@ float64 __attribute__((flatten)) float64_mul(float64 a, float64 b,
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return float64_round_pack_canonical(pr, status);
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return float64_round_pack_canonical(pr, status);
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}
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}
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/*
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* Returns the result of multiplying the floating-point values `a' and
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* `b' then adding 'c', with no intermediate rounding step after the
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* multiplication. The operation is performed according to the
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* IEC/IEEE Standard for Binary Floating-Point Arithmetic 754-2008.
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* The flags argument allows the caller to select negation of the
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* addend, the intermediate product, or the final result. (The
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* difference between this and having the caller do a separate
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* negation is that negating externally will flip the sign bit on
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* NaNs.)
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*/
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static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c,
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int flags, float_status *s)
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{
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bool inf_zero = ((1 << a.cls) | (1 << b.cls)) ==
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((1 << float_class_inf) | (1 << float_class_zero));
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bool p_sign;
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bool sign_flip = flags & float_muladd_negate_result;
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FloatClass p_class;
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uint64_t hi, lo;
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int p_exp;
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/* It is implementation-defined whether the cases of (0,inf,qnan)
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* and (inf,0,qnan) raise InvalidOperation or not (and what QNaN
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* they return if they do), so we have to hand this information
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* off to the target-specific pick-a-NaN routine.
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*/
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if (is_nan(a.cls) || is_nan(b.cls) || is_nan(c.cls)) {
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return pick_nan_muladd(a, b, c, inf_zero, s);
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}
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if (inf_zero) {
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s->float_exception_flags |= float_flag_invalid;
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a.cls = float_class_dnan;
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return a;
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}
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if (flags & float_muladd_negate_c) {
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c.sign ^= 1;
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}
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p_sign = a.sign ^ b.sign;
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if (flags & float_muladd_negate_product) {
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p_sign ^= 1;
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}
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if (a.cls == float_class_inf || b.cls == float_class_inf) {
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p_class = float_class_inf;
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} else if (a.cls == float_class_zero || b.cls == float_class_zero) {
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p_class = float_class_zero;
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} else {
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p_class = float_class_normal;
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}
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if (c.cls == float_class_inf) {
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if (p_class == float_class_inf && p_sign != c.sign) {
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s->float_exception_flags |= float_flag_invalid;
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a.cls = float_class_dnan;
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} else {
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a.cls = float_class_inf;
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a.sign = c.sign ^ sign_flip;
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}
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return a;
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}
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if (p_class == float_class_inf) {
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a.cls = float_class_inf;
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a.sign = p_sign ^ sign_flip;
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return a;
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}
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if (p_class == float_class_zero) {
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if (c.cls == float_class_zero) {
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if (p_sign != c.sign) {
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p_sign = s->float_rounding_mode == float_round_down;
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}
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c.sign = p_sign;
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} else if (flags & float_muladd_halve_result) {
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c.exp -= 1;
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}
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c.sign ^= sign_flip;
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return c;
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}
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/* a & b should be normals now... */
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assert(a.cls == float_class_normal &&
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b.cls == float_class_normal);
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p_exp = a.exp + b.exp;
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/* Multiply of 2 62-bit numbers produces a (2*62) == 124-bit
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* result.
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*/
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mul64To128(a.frac, b.frac, &hi, &lo);
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/* binary point now at bit 124 */
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/* check for overflow */
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if (hi & (1ULL << (DECOMPOSED_BINARY_POINT * 2 + 1 - 64))) {
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shift128RightJamming(hi, lo, 1, &hi, &lo);
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p_exp += 1;
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}
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/* + add/sub */
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if (c.cls == float_class_zero) {
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/* move binary point back to 62 */
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shift128RightJamming(hi, lo, DECOMPOSED_BINARY_POINT, &hi, &lo);
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} else {
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int exp_diff = p_exp - c.exp;
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if (p_sign == c.sign) {
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/* Addition */
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if (exp_diff <= 0) {
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shift128RightJamming(hi, lo,
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DECOMPOSED_BINARY_POINT - exp_diff,
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&hi, &lo);
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lo += c.frac;
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p_exp = c.exp;
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} else {
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uint64_t c_hi, c_lo;
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/* shift c to the same binary point as the product (124) */
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c_hi = c.frac >> 2;
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c_lo = 0;
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shift128RightJamming(c_hi, c_lo,
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exp_diff,
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&c_hi, &c_lo);
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add128(hi, lo, c_hi, c_lo, &hi, &lo);
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/* move binary point back to 62 */
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shift128RightJamming(hi, lo, DECOMPOSED_BINARY_POINT, &hi, &lo);
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}
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if (lo & DECOMPOSED_OVERFLOW_BIT) {
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shift64RightJamming(lo, 1, &lo);
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p_exp += 1;
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}
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} else {
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/* Subtraction */
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uint64_t c_hi, c_lo;
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/* make C binary point match product at bit 124 */
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c_hi = c.frac >> 2;
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c_lo = 0;
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if (exp_diff <= 0) {
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shift128RightJamming(hi, lo, -exp_diff, &hi, &lo);
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if (exp_diff == 0
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&&
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(hi > c_hi || (hi == c_hi && lo >= c_lo))) {
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sub128(hi, lo, c_hi, c_lo, &hi, &lo);
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} else {
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sub128(c_hi, c_lo, hi, lo, &hi, &lo);
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p_sign ^= 1;
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p_exp = c.exp;
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}
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} else {
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shift128RightJamming(c_hi, c_lo,
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exp_diff,
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&c_hi, &c_lo);
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sub128(hi, lo, c_hi, c_lo, &hi, &lo);
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}
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if (hi == 0 && lo == 0) {
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a.cls = float_class_zero;
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a.sign = s->float_rounding_mode == float_round_down;
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a.sign ^= sign_flip;
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return a;
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} else {
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int shift;
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if (hi != 0) {
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shift = clz64(hi);
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} else {
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shift = clz64(lo) + 64;
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}
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/* Normalizing to a binary point of 124 is the
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correct adjust for the exponent. However since we're
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shifting, we might as well put the binary point back
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at 62 where we really want it. Therefore shift as
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if we're leaving 1 bit at the top of the word, but
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adjust the exponent as if we're leaving 3 bits. */
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shift -= 1;
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if (shift >= 64) {
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lo = lo << (shift - 64);
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} else {
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hi = (hi << shift) | (lo >> (64 - shift));
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lo = hi | ((lo << shift) != 0);
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}
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p_exp -= shift - 2;
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}
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}
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}
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if (flags & float_muladd_halve_result) {
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p_exp -= 1;
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}
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/* finally prepare our result */
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a.cls = float_class_normal;
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a.sign = p_sign ^ sign_flip;
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a.exp = p_exp;
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a.frac = lo;
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|
||||||
|
return a;
|
||||||
|
}
|
||||||
|
|
||||||
|
float16 __attribute__((flatten)) float16_muladd(float16 a, float16 b, float16 c,
|
||||||
|
int flags, float_status *status)
|
||||||
|
{
|
||||||
|
FloatParts pa = float16_unpack_canonical(a, status);
|
||||||
|
FloatParts pb = float16_unpack_canonical(b, status);
|
||||||
|
FloatParts pc = float16_unpack_canonical(c, status);
|
||||||
|
FloatParts pr = muladd_floats(pa, pb, pc, flags, status);
|
||||||
|
|
||||||
|
return float16_round_pack_canonical(pr, status);
|
||||||
|
}
|
||||||
|
|
||||||
|
float32 __attribute__((flatten)) float32_muladd(float32 a, float32 b, float32 c,
|
||||||
|
int flags, float_status *status)
|
||||||
|
{
|
||||||
|
FloatParts pa = float32_unpack_canonical(a, status);
|
||||||
|
FloatParts pb = float32_unpack_canonical(b, status);
|
||||||
|
FloatParts pc = float32_unpack_canonical(c, status);
|
||||||
|
FloatParts pr = muladd_floats(pa, pb, pc, flags, status);
|
||||||
|
|
||||||
|
return float32_round_pack_canonical(pr, status);
|
||||||
|
}
|
||||||
|
|
||||||
|
float64 __attribute__((flatten)) float64_muladd(float64 a, float64 b, float64 c,
|
||||||
|
int flags, float_status *status)
|
||||||
|
{
|
||||||
|
FloatParts pa = float64_unpack_canonical(a, status);
|
||||||
|
FloatParts pb = float64_unpack_canonical(b, status);
|
||||||
|
FloatParts pc = float64_unpack_canonical(c, status);
|
||||||
|
FloatParts pr = muladd_floats(pa, pb, pc, flags, status);
|
||||||
|
|
||||||
|
return float64_round_pack_canonical(pr, status);
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Returns the result of dividing the floating-point value `a' by the
|
* Returns the result of dividing the floating-point value `a' by the
|
||||||
* corresponding value `b'. The operation is performed according to
|
* corresponding value `b'. The operation is performed according to
|
||||||
@ -2817,231 +3088,6 @@ float32 float32_rem(float32 a, float32 b, float_status *status)
|
|||||||
return normalizeRoundAndPackFloat32(aSign ^ zSign, bExp, aSig, status);
|
return normalizeRoundAndPackFloat32(aSign ^ zSign, bExp, aSig, status);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------
|
|
||||||
| Returns the result of multiplying the single-precision floating-point values
|
|
||||||
| `a' and `b' then adding 'c', with no intermediate rounding step after the
|
|
||||||
| multiplication. The operation is performed according to the IEC/IEEE
|
|
||||||
| Standard for Binary Floating-Point Arithmetic 754-2008.
|
|
||||||
| The flags argument allows the caller to select negation of the
|
|
||||||
| addend, the intermediate product, or the final result. (The difference
|
|
||||||
| between this and having the caller do a separate negation is that negating
|
|
||||||
| externally will flip the sign bit on NaNs.)
|
|
||||||
*----------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
float32 float32_muladd(float32 a, float32 b, float32 c, int flags,
|
|
||||||
float_status *status)
|
|
||||||
{
|
|
||||||
flag aSign, bSign, cSign, zSign;
|
|
||||||
int aExp, bExp, cExp, pExp, zExp, expDiff;
|
|
||||||
uint32_t aSig, bSig, cSig;
|
|
||||||
flag pInf, pZero, pSign;
|
|
||||||
uint64_t pSig64, cSig64, zSig64;
|
|
||||||
uint32_t pSig;
|
|
||||||
int shiftcount;
|
|
||||||
flag signflip, infzero;
|
|
||||||
|
|
||||||
a = float32_squash_input_denormal(a, status);
|
|
||||||
b = float32_squash_input_denormal(b, status);
|
|
||||||
c = float32_squash_input_denormal(c, status);
|
|
||||||
aSig = extractFloat32Frac(a);
|
|
||||||
aExp = extractFloat32Exp(a);
|
|
||||||
aSign = extractFloat32Sign(a);
|
|
||||||
bSig = extractFloat32Frac(b);
|
|
||||||
bExp = extractFloat32Exp(b);
|
|
||||||
bSign = extractFloat32Sign(b);
|
|
||||||
cSig = extractFloat32Frac(c);
|
|
||||||
cExp = extractFloat32Exp(c);
|
|
||||||
cSign = extractFloat32Sign(c);
|
|
||||||
|
|
||||||
infzero = ((aExp == 0 && aSig == 0 && bExp == 0xff && bSig == 0) ||
|
|
||||||
(aExp == 0xff && aSig == 0 && bExp == 0 && bSig == 0));
|
|
||||||
|
|
||||||
/* It is implementation-defined whether the cases of (0,inf,qnan)
|
|
||||||
* and (inf,0,qnan) raise InvalidOperation or not (and what QNaN
|
|
||||||
* they return if they do), so we have to hand this information
|
|
||||||
* off to the target-specific pick-a-NaN routine.
|
|
||||||
*/
|
|
||||||
if (((aExp == 0xff) && aSig) ||
|
|
||||||
((bExp == 0xff) && bSig) ||
|
|
||||||
((cExp == 0xff) && cSig)) {
|
|
||||||
return propagateFloat32MulAddNaN(a, b, c, infzero, status);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (infzero) {
|
|
||||||
float_raise(float_flag_invalid, status);
|
|
||||||
return float32_default_nan(status);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (flags & float_muladd_negate_c) {
|
|
||||||
cSign ^= 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
signflip = (flags & float_muladd_negate_result) ? 1 : 0;
|
|
||||||
|
|
||||||
/* Work out the sign and type of the product */
|
|
||||||
pSign = aSign ^ bSign;
|
|
||||||
if (flags & float_muladd_negate_product) {
|
|
||||||
pSign ^= 1;
|
|
||||||
}
|
|
||||||
pInf = (aExp == 0xff) || (bExp == 0xff);
|
|
||||||
pZero = ((aExp | aSig) == 0) || ((bExp | bSig) == 0);
|
|
||||||
|
|
||||||
if (cExp == 0xff) {
|
|
||||||
if (pInf && (pSign ^ cSign)) {
|
|
||||||
/* addition of opposite-signed infinities => InvalidOperation */
|
|
||||||
float_raise(float_flag_invalid, status);
|
|
||||||
return float32_default_nan(status);
|
|
||||||
}
|
|
||||||
/* Otherwise generate an infinity of the same sign */
|
|
||||||
return packFloat32(cSign ^ signflip, 0xff, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (pInf) {
|
|
||||||
return packFloat32(pSign ^ signflip, 0xff, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (pZero) {
|
|
||||||
if (cExp == 0) {
|
|
||||||
if (cSig == 0) {
|
|
||||||
/* Adding two exact zeroes */
|
|
||||||
if (pSign == cSign) {
|
|
||||||
zSign = pSign;
|
|
||||||
} else if (status->float_rounding_mode == float_round_down) {
|
|
||||||
zSign = 1;
|
|
||||||
} else {
|
|
||||||
zSign = 0;
|
|
||||||
}
|
|
||||||
return packFloat32(zSign ^ signflip, 0, 0);
|
|
||||||
}
|
|
||||||
/* Exact zero plus a denorm */
|
|
||||||
if (status->flush_to_zero) {
|
|
||||||
float_raise(float_flag_output_denormal, status);
|
|
||||||
return packFloat32(cSign ^ signflip, 0, 0);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/* Zero plus something non-zero : just return the something */
|
|
||||||
if (flags & float_muladd_halve_result) {
|
|
||||||
if (cExp == 0) {
|
|
||||||
normalizeFloat32Subnormal(cSig, &cExp, &cSig);
|
|
||||||
}
|
|
||||||
/* Subtract one to halve, and one again because roundAndPackFloat32
|
|
||||||
* wants one less than the true exponent.
|
|
||||||
*/
|
|
||||||
cExp -= 2;
|
|
||||||
cSig = (cSig | 0x00800000) << 7;
|
|
||||||
return roundAndPackFloat32(cSign ^ signflip, cExp, cSig, status);
|
|
||||||
}
|
|
||||||
return packFloat32(cSign ^ signflip, cExp, cSig);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (aExp == 0) {
|
|
||||||
normalizeFloat32Subnormal(aSig, &aExp, &aSig);
|
|
||||||
}
|
|
||||||
if (bExp == 0) {
|
|
||||||
normalizeFloat32Subnormal(bSig, &bExp, &bSig);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Calculate the actual result a * b + c */
|
|
||||||
|
|
||||||
/* Multiply first; this is easy. */
|
|
||||||
/* NB: we subtract 0x7e where float32_mul() subtracts 0x7f
|
|
||||||
* because we want the true exponent, not the "one-less-than"
|
|
||||||
* flavour that roundAndPackFloat32() takes.
|
|
||||||
*/
|
|
||||||
pExp = aExp + bExp - 0x7e;
|
|
||||||
aSig = (aSig | 0x00800000) << 7;
|
|
||||||
bSig = (bSig | 0x00800000) << 8;
|
|
||||||
pSig64 = (uint64_t)aSig * bSig;
|
|
||||||
if ((int64_t)(pSig64 << 1) >= 0) {
|
|
||||||
pSig64 <<= 1;
|
|
||||||
pExp--;
|
|
||||||
}
|
|
||||||
|
|
||||||
zSign = pSign ^ signflip;
|
|
||||||
|
|
||||||
/* Now pSig64 is the significand of the multiply, with the explicit bit in
|
|
||||||
* position 62.
|
|
||||||
*/
|
|
||||||
if (cExp == 0) {
|
|
||||||
if (!cSig) {
|
|
||||||
/* Throw out the special case of c being an exact zero now */
|
|
||||||
shift64RightJamming(pSig64, 32, &pSig64);
|
|
||||||
pSig = pSig64;
|
|
||||||
if (flags & float_muladd_halve_result) {
|
|
||||||
pExp--;
|
|
||||||
}
|
|
||||||
return roundAndPackFloat32(zSign, pExp - 1,
|
|
||||||
pSig, status);
|
|
||||||
}
|
|
||||||
normalizeFloat32Subnormal(cSig, &cExp, &cSig);
|
|
||||||
}
|
|
||||||
|
|
||||||
cSig64 = (uint64_t)cSig << (62 - 23);
|
|
||||||
cSig64 |= LIT64(0x4000000000000000);
|
|
||||||
expDiff = pExp - cExp;
|
|
||||||
|
|
||||||
if (pSign == cSign) {
|
|
||||||
/* Addition */
|
|
||||||
if (expDiff > 0) {
|
|
||||||
/* scale c to match p */
|
|
||||||
shift64RightJamming(cSig64, expDiff, &cSig64);
|
|
||||||
zExp = pExp;
|
|
||||||
} else if (expDiff < 0) {
|
|
||||||
/* scale p to match c */
|
|
||||||
shift64RightJamming(pSig64, -expDiff, &pSig64);
|
|
||||||
zExp = cExp;
|
|
||||||
} else {
|
|
||||||
/* no scaling needed */
|
|
||||||
zExp = cExp;
|
|
||||||
}
|
|
||||||
/* Add significands and make sure explicit bit ends up in posn 62 */
|
|
||||||
zSig64 = pSig64 + cSig64;
|
|
||||||
if ((int64_t)zSig64 < 0) {
|
|
||||||
shift64RightJamming(zSig64, 1, &zSig64);
|
|
||||||
} else {
|
|
||||||
zExp--;
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
/* Subtraction */
|
|
||||||
if (expDiff > 0) {
|
|
||||||
shift64RightJamming(cSig64, expDiff, &cSig64);
|
|
||||||
zSig64 = pSig64 - cSig64;
|
|
||||||
zExp = pExp;
|
|
||||||
} else if (expDiff < 0) {
|
|
||||||
shift64RightJamming(pSig64, -expDiff, &pSig64);
|
|
||||||
zSig64 = cSig64 - pSig64;
|
|
||||||
zExp = cExp;
|
|
||||||
zSign ^= 1;
|
|
||||||
} else {
|
|
||||||
zExp = pExp;
|
|
||||||
if (cSig64 < pSig64) {
|
|
||||||
zSig64 = pSig64 - cSig64;
|
|
||||||
} else if (pSig64 < cSig64) {
|
|
||||||
zSig64 = cSig64 - pSig64;
|
|
||||||
zSign ^= 1;
|
|
||||||
} else {
|
|
||||||
/* Exact zero */
|
|
||||||
zSign = signflip;
|
|
||||||
if (status->float_rounding_mode == float_round_down) {
|
|
||||||
zSign ^= 1;
|
|
||||||
}
|
|
||||||
return packFloat32(zSign, 0, 0);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
--zExp;
|
|
||||||
/* Normalize to put the explicit bit back into bit 62. */
|
|
||||||
shiftcount = countLeadingZeros64(zSig64) - 1;
|
|
||||||
zSig64 <<= shiftcount;
|
|
||||||
zExp -= shiftcount;
|
|
||||||
}
|
|
||||||
if (flags & float_muladd_halve_result) {
|
|
||||||
zExp--;
|
|
||||||
}
|
|
||||||
|
|
||||||
shift64RightJamming(zSig64, 32, &zSig64);
|
|
||||||
return roundAndPackFloat32(zSign, zExp, zSig64, status);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------
|
/*----------------------------------------------------------------------------
|
||||||
| Returns the square root of the single-precision floating-point value `a'.
|
| Returns the square root of the single-precision floating-point value `a'.
|
||||||
@ -4265,252 +4311,6 @@ float64 float64_rem(float64 a, float64 b, float_status *status)
|
|||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------
|
|
||||||
| Returns the result of multiplying the double-precision floating-point values
|
|
||||||
| `a' and `b' then adding 'c', with no intermediate rounding step after the
|
|
||||||
| multiplication. The operation is performed according to the IEC/IEEE
|
|
||||||
| Standard for Binary Floating-Point Arithmetic 754-2008.
|
|
||||||
| The flags argument allows the caller to select negation of the
|
|
||||||
| addend, the intermediate product, or the final result. (The difference
|
|
||||||
| between this and having the caller do a separate negation is that negating
|
|
||||||
| externally will flip the sign bit on NaNs.)
|
|
||||||
*----------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
float64 float64_muladd(float64 a, float64 b, float64 c, int flags,
|
|
||||||
float_status *status)
|
|
||||||
{
|
|
||||||
flag aSign, bSign, cSign, zSign;
|
|
||||||
int aExp, bExp, cExp, pExp, zExp, expDiff;
|
|
||||||
uint64_t aSig, bSig, cSig;
|
|
||||||
flag pInf, pZero, pSign;
|
|
||||||
uint64_t pSig0, pSig1, cSig0, cSig1, zSig0, zSig1;
|
|
||||||
int shiftcount;
|
|
||||||
flag signflip, infzero;
|
|
||||||
|
|
||||||
a = float64_squash_input_denormal(a, status);
|
|
||||||
b = float64_squash_input_denormal(b, status);
|
|
||||||
c = float64_squash_input_denormal(c, status);
|
|
||||||
aSig = extractFloat64Frac(a);
|
|
||||||
aExp = extractFloat64Exp(a);
|
|
||||||
aSign = extractFloat64Sign(a);
|
|
||||||
bSig = extractFloat64Frac(b);
|
|
||||||
bExp = extractFloat64Exp(b);
|
|
||||||
bSign = extractFloat64Sign(b);
|
|
||||||
cSig = extractFloat64Frac(c);
|
|
||||||
cExp = extractFloat64Exp(c);
|
|
||||||
cSign = extractFloat64Sign(c);
|
|
||||||
|
|
||||||
infzero = ((aExp == 0 && aSig == 0 && bExp == 0x7ff && bSig == 0) ||
|
|
||||||
(aExp == 0x7ff && aSig == 0 && bExp == 0 && bSig == 0));
|
|
||||||
|
|
||||||
/* It is implementation-defined whether the cases of (0,inf,qnan)
|
|
||||||
* and (inf,0,qnan) raise InvalidOperation or not (and what QNaN
|
|
||||||
* they return if they do), so we have to hand this information
|
|
||||||
* off to the target-specific pick-a-NaN routine.
|
|
||||||
*/
|
|
||||||
if (((aExp == 0x7ff) && aSig) ||
|
|
||||||
((bExp == 0x7ff) && bSig) ||
|
|
||||||
((cExp == 0x7ff) && cSig)) {
|
|
||||||
return propagateFloat64MulAddNaN(a, b, c, infzero, status);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (infzero) {
|
|
||||||
float_raise(float_flag_invalid, status);
|
|
||||||
return float64_default_nan(status);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (flags & float_muladd_negate_c) {
|
|
||||||
cSign ^= 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
signflip = (flags & float_muladd_negate_result) ? 1 : 0;
|
|
||||||
|
|
||||||
/* Work out the sign and type of the product */
|
|
||||||
pSign = aSign ^ bSign;
|
|
||||||
if (flags & float_muladd_negate_product) {
|
|
||||||
pSign ^= 1;
|
|
||||||
}
|
|
||||||
pInf = (aExp == 0x7ff) || (bExp == 0x7ff);
|
|
||||||
pZero = ((aExp | aSig) == 0) || ((bExp | bSig) == 0);
|
|
||||||
|
|
||||||
if (cExp == 0x7ff) {
|
|
||||||
if (pInf && (pSign ^ cSign)) {
|
|
||||||
/* addition of opposite-signed infinities => InvalidOperation */
|
|
||||||
float_raise(float_flag_invalid, status);
|
|
||||||
return float64_default_nan(status);
|
|
||||||
}
|
|
||||||
/* Otherwise generate an infinity of the same sign */
|
|
||||||
return packFloat64(cSign ^ signflip, 0x7ff, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (pInf) {
|
|
||||||
return packFloat64(pSign ^ signflip, 0x7ff, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (pZero) {
|
|
||||||
if (cExp == 0) {
|
|
||||||
if (cSig == 0) {
|
|
||||||
/* Adding two exact zeroes */
|
|
||||||
if (pSign == cSign) {
|
|
||||||
zSign = pSign;
|
|
||||||
} else if (status->float_rounding_mode == float_round_down) {
|
|
||||||
zSign = 1;
|
|
||||||
} else {
|
|
||||||
zSign = 0;
|
|
||||||
}
|
|
||||||
return packFloat64(zSign ^ signflip, 0, 0);
|
|
||||||
}
|
|
||||||
/* Exact zero plus a denorm */
|
|
||||||
if (status->flush_to_zero) {
|
|
||||||
float_raise(float_flag_output_denormal, status);
|
|
||||||
return packFloat64(cSign ^ signflip, 0, 0);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/* Zero plus something non-zero : just return the something */
|
|
||||||
if (flags & float_muladd_halve_result) {
|
|
||||||
if (cExp == 0) {
|
|
||||||
normalizeFloat64Subnormal(cSig, &cExp, &cSig);
|
|
||||||
}
|
|
||||||
/* Subtract one to halve, and one again because roundAndPackFloat64
|
|
||||||
* wants one less than the true exponent.
|
|
||||||
*/
|
|
||||||
cExp -= 2;
|
|
||||||
cSig = (cSig | 0x0010000000000000ULL) << 10;
|
|
||||||
return roundAndPackFloat64(cSign ^ signflip, cExp, cSig, status);
|
|
||||||
}
|
|
||||||
return packFloat64(cSign ^ signflip, cExp, cSig);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (aExp == 0) {
|
|
||||||
normalizeFloat64Subnormal(aSig, &aExp, &aSig);
|
|
||||||
}
|
|
||||||
if (bExp == 0) {
|
|
||||||
normalizeFloat64Subnormal(bSig, &bExp, &bSig);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Calculate the actual result a * b + c */
|
|
||||||
|
|
||||||
/* Multiply first; this is easy. */
|
|
||||||
/* NB: we subtract 0x3fe where float64_mul() subtracts 0x3ff
|
|
||||||
* because we want the true exponent, not the "one-less-than"
|
|
||||||
* flavour that roundAndPackFloat64() takes.
|
|
||||||
*/
|
|
||||||
pExp = aExp + bExp - 0x3fe;
|
|
||||||
aSig = (aSig | LIT64(0x0010000000000000))<<10;
|
|
||||||
bSig = (bSig | LIT64(0x0010000000000000))<<11;
|
|
||||||
mul64To128(aSig, bSig, &pSig0, &pSig1);
|
|
||||||
if ((int64_t)(pSig0 << 1) >= 0) {
|
|
||||||
shortShift128Left(pSig0, pSig1, 1, &pSig0, &pSig1);
|
|
||||||
pExp--;
|
|
||||||
}
|
|
||||||
|
|
||||||
zSign = pSign ^ signflip;
|
|
||||||
|
|
||||||
/* Now [pSig0:pSig1] is the significand of the multiply, with the explicit
|
|
||||||
* bit in position 126.
|
|
||||||
*/
|
|
||||||
if (cExp == 0) {
|
|
||||||
if (!cSig) {
|
|
||||||
/* Throw out the special case of c being an exact zero now */
|
|
||||||
shift128RightJamming(pSig0, pSig1, 64, &pSig0, &pSig1);
|
|
||||||
if (flags & float_muladd_halve_result) {
|
|
||||||
pExp--;
|
|
||||||
}
|
|
||||||
return roundAndPackFloat64(zSign, pExp - 1,
|
|
||||||
pSig1, status);
|
|
||||||
}
|
|
||||||
normalizeFloat64Subnormal(cSig, &cExp, &cSig);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Shift cSig and add the explicit bit so [cSig0:cSig1] is the
|
|
||||||
* significand of the addend, with the explicit bit in position 126.
|
|
||||||
*/
|
|
||||||
cSig0 = cSig << (126 - 64 - 52);
|
|
||||||
cSig1 = 0;
|
|
||||||
cSig0 |= LIT64(0x4000000000000000);
|
|
||||||
expDiff = pExp - cExp;
|
|
||||||
|
|
||||||
if (pSign == cSign) {
|
|
||||||
/* Addition */
|
|
||||||
if (expDiff > 0) {
|
|
||||||
/* scale c to match p */
|
|
||||||
shift128RightJamming(cSig0, cSig1, expDiff, &cSig0, &cSig1);
|
|
||||||
zExp = pExp;
|
|
||||||
} else if (expDiff < 0) {
|
|
||||||
/* scale p to match c */
|
|
||||||
shift128RightJamming(pSig0, pSig1, -expDiff, &pSig0, &pSig1);
|
|
||||||
zExp = cExp;
|
|
||||||
} else {
|
|
||||||
/* no scaling needed */
|
|
||||||
zExp = cExp;
|
|
||||||
}
|
|
||||||
/* Add significands and make sure explicit bit ends up in posn 126 */
|
|
||||||
add128(pSig0, pSig1, cSig0, cSig1, &zSig0, &zSig1);
|
|
||||||
if ((int64_t)zSig0 < 0) {
|
|
||||||
shift128RightJamming(zSig0, zSig1, 1, &zSig0, &zSig1);
|
|
||||||
} else {
|
|
||||||
zExp--;
|
|
||||||
}
|
|
||||||
shift128RightJamming(zSig0, zSig1, 64, &zSig0, &zSig1);
|
|
||||||
if (flags & float_muladd_halve_result) {
|
|
||||||
zExp--;
|
|
||||||
}
|
|
||||||
return roundAndPackFloat64(zSign, zExp, zSig1, status);
|
|
||||||
} else {
|
|
||||||
/* Subtraction */
|
|
||||||
if (expDiff > 0) {
|
|
||||||
shift128RightJamming(cSig0, cSig1, expDiff, &cSig0, &cSig1);
|
|
||||||
sub128(pSig0, pSig1, cSig0, cSig1, &zSig0, &zSig1);
|
|
||||||
zExp = pExp;
|
|
||||||
} else if (expDiff < 0) {
|
|
||||||
shift128RightJamming(pSig0, pSig1, -expDiff, &pSig0, &pSig1);
|
|
||||||
sub128(cSig0, cSig1, pSig0, pSig1, &zSig0, &zSig1);
|
|
||||||
zExp = cExp;
|
|
||||||
zSign ^= 1;
|
|
||||||
} else {
|
|
||||||
zExp = pExp;
|
|
||||||
if (lt128(cSig0, cSig1, pSig0, pSig1)) {
|
|
||||||
sub128(pSig0, pSig1, cSig0, cSig1, &zSig0, &zSig1);
|
|
||||||
} else if (lt128(pSig0, pSig1, cSig0, cSig1)) {
|
|
||||||
sub128(cSig0, cSig1, pSig0, pSig1, &zSig0, &zSig1);
|
|
||||||
zSign ^= 1;
|
|
||||||
} else {
|
|
||||||
/* Exact zero */
|
|
||||||
zSign = signflip;
|
|
||||||
if (status->float_rounding_mode == float_round_down) {
|
|
||||||
zSign ^= 1;
|
|
||||||
}
|
|
||||||
return packFloat64(zSign, 0, 0);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
--zExp;
|
|
||||||
/* Do the equivalent of normalizeRoundAndPackFloat64() but
|
|
||||||
* starting with the significand in a pair of uint64_t.
|
|
||||||
*/
|
|
||||||
if (zSig0) {
|
|
||||||
shiftcount = countLeadingZeros64(zSig0) - 1;
|
|
||||||
shortShift128Left(zSig0, zSig1, shiftcount, &zSig0, &zSig1);
|
|
||||||
if (zSig1) {
|
|
||||||
zSig0 |= 1;
|
|
||||||
}
|
|
||||||
zExp -= shiftcount;
|
|
||||||
} else {
|
|
||||||
shiftcount = countLeadingZeros64(zSig1);
|
|
||||||
if (shiftcount == 0) {
|
|
||||||
zSig0 = (zSig1 >> 1) | (zSig1 & 1);
|
|
||||||
zExp -= 63;
|
|
||||||
} else {
|
|
||||||
shiftcount--;
|
|
||||||
zSig0 = zSig1 << shiftcount;
|
|
||||||
zExp -= (shiftcount + 64);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (flags & float_muladd_halve_result) {
|
|
||||||
zExp--;
|
|
||||||
}
|
|
||||||
return roundAndPackFloat64(zSign, zExp, zSig0, status);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*----------------------------------------------------------------------------
|
/*----------------------------------------------------------------------------
|
||||||
| Returns the square root of the double-precision floating-point value `a'.
|
| Returns the square root of the double-precision floating-point value `a'.
|
||||||
|
|||||||
@ -240,6 +240,7 @@ float64 float16_to_float64(float16 a, flag ieee, float_status *status);
|
|||||||
float16 float16_add(float16, float16, float_status *status);
|
float16 float16_add(float16, float16, float_status *status);
|
||||||
float16 float16_sub(float16, float16, float_status *status);
|
float16 float16_sub(float16, float16, float_status *status);
|
||||||
float16 float16_mul(float16, float16, float_status *status);
|
float16 float16_mul(float16, float16, float_status *status);
|
||||||
|
float16 float16_muladd(float16, float16, float16, int, float_status *status);
|
||||||
float16 float16_div(float16, float16, float_status *status);
|
float16 float16_div(float16, float16, float_status *status);
|
||||||
|
|
||||||
int float16_is_quiet_nan(float16, float_status *status);
|
int float16_is_quiet_nan(float16, float_status *status);
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user