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use simpler REGPARM convention - make CPUTLBEntry size a power of two

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3935 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard 2008-01-31 09:22:27 +00:00
parent 0019ad5346
commit d656469f44
4 changed files with 28 additions and 17 deletions
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16
cpu-defs.h
View File

@ -102,6 +102,12 @@ typedef unsigned long ram_addr_t;
#define CPU_TLB_BITS 8
#define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
#if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32
#define CPU_TLB_ENTRY_BITS 4
#else
#define CPU_TLB_ENTRY_BITS 5
#endif
typedef struct CPUTLBEntry {
/* bit 31 to TARGET_PAGE_BITS : virtual address
bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io
@ -113,7 +119,17 @@ typedef struct CPUTLBEntry {
target_ulong addr_write;
target_ulong addr_code;
/* addend to virtual address to get physical address */
#if TARGET_PHYS_ADDR_BITS == 64
/* on i386 Linux make sure it is aligned */
target_phys_addr_t addend __attribute__((aligned(8)));
#else
target_phys_addr_t addend;
#endif
/* padding to get a power of two size */
uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
(sizeof(target_ulong) * 3 +
((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) +
sizeof(target_phys_addr_t))];
} CPUTLBEntry;
#define CPU_COMMON \

4
osdep.h
View File

@ -36,9 +36,9 @@
#define inline always_inline
#ifdef __i386__
#define REGPARM(n) __attribute((regparm(n)))
#define REGPARM __attribute((regparm(3)))
#else
#define REGPARM(n)
#define REGPARM
#endif
#define qemu_printf printf

15
softmmu_header.h
View File

@ -70,15 +70,13 @@
#define ADDR_READ addr_read
#endif
DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
int mmu_idx);
void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int mmu_idx);
void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int mmu_idx);
#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
(ACCESS_TYPE < NB_MMU_MODES) && defined(ASM_SOFTMMU)
#define CPU_TLB_ENTRY_BITS 4
static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
{
int res;
@ -92,9 +90,8 @@ static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
"cmpl (%%edx), %%eax\n"
"movl %1, %%eax\n"
"je 1f\n"
"pushl %6\n"
"movl %6, %%edx\n"
"call %7\n"
"popl %%edx\n"
"movl %%eax, %0\n"
"jmp 2f\n"
"1:\n"
@ -135,9 +132,8 @@ static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
"cmpl (%%edx), %%eax\n"
"movl %1, %%eax\n"
"je 1f\n"
"pushl %6\n"
"movl %6, %%edx\n"
"call %7\n"
"popl %%edx\n"
#if DATA_SIZE == 1
"movsbl %%al, %0\n"
#elif DATA_SIZE == 2
@ -189,9 +185,8 @@ static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE
#else
#error unsupported size
#endif
"pushl %6\n"
"movl %6, %%ecx\n"
"call %7\n"
"popl %%eax\n"
"jmp 2f\n"
"1:\n"
"addl 8(%%edx), %%eax\n"

10
softmmu_template.h
View File

@ -75,8 +75,8 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
}
/* handle all cases except unaligned access which span two pages */
DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
int mmu_idx)
DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
int mmu_idx)
{
DATA_TYPE res;
int index;
@ -209,9 +209,9 @@ static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
#endif
}
void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
DATA_TYPE val,
int mmu_idx)
void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
DATA_TYPE val,
int mmu_idx)
{
target_phys_addr_t physaddr;
target_ulong tlb_addr;