monitor: implement x86 info tlb for PAE and long modes
'info tlb' didn't show correct information for PAE mode and x86_64 long mode. Implement the missing modes. Also print NX bit for PAE and long modes. Fix off-by-one error in 32 bit mode mask. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl
parent
fa82e9c300
commit
d65aaf3773
151
monitor.c
151
monitor.c
@ -1848,11 +1848,20 @@ static int do_system_powerdown(Monitor *mon, const QDict *qdict,
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}
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#if defined(TARGET_I386)
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static void print_pte(Monitor *mon, uint32_t addr, uint32_t pte, uint32_t mask)
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static void print_pte(Monitor *mon, target_phys_addr_t addr,
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target_phys_addr_t pte,
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target_phys_addr_t mask)
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{
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monitor_printf(mon, "%08x: %08x %c%c%c%c%c%c%c%c\n",
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#ifdef TARGET_X86_64
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if (addr & (1ULL << 47)) {
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addr |= -1LL << 48;
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}
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#endif
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monitor_printf(mon, TARGET_FMT_plx ": " TARGET_FMT_plx
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" %c%c%c%c%c%c%c%c%c\n",
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addr,
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pte & mask,
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pte & PG_NX_MASK ? 'X' : '-',
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pte & PG_GLOBAL_MASK ? 'G' : '-',
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pte & PG_PSE_MASK ? 'P' : '-',
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pte & PG_DIRTY_MASK ? 'D' : '-',
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@ -1863,25 +1872,19 @@ static void print_pte(Monitor *mon, uint32_t addr, uint32_t pte, uint32_t mask)
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pte & PG_RW_MASK ? 'W' : '-');
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}
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static void tlb_info(Monitor *mon)
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static void tlb_info_32(Monitor *mon, CPUState *env)
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{
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CPUState *env;
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int l1, l2;
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uint32_t pgd, pde, pte;
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env = mon_get_cpu();
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if (!(env->cr[0] & CR0_PG_MASK)) {
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monitor_printf(mon, "PG disabled\n");
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return;
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}
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pgd = env->cr[3] & ~0xfff;
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for(l1 = 0; l1 < 1024; l1++) {
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cpu_physical_memory_read(pgd + l1 * 4, (uint8_t *)&pde, 4);
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pde = le32_to_cpu(pde);
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if (pde & PG_PRESENT_MASK) {
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if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
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print_pte(mon, (l1 << 22), pde, ~((1 << 20) - 1));
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/* 4M pages */
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print_pte(mon, (l1 << 22), pde, ~((1 << 21) - 1));
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} else {
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for(l2 = 0; l2 < 1024; l2++) {
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cpu_physical_memory_read((pde & ~0xfff) + l2 * 4,
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@ -1898,6 +1901,132 @@ static void tlb_info(Monitor *mon)
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}
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}
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static void tlb_info_pae32(Monitor *mon, CPUState *env)
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{
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int l1, l2, l3;
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uint64_t pdpe, pde, pte;
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uint64_t pdp_addr, pd_addr, pt_addr;
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pdp_addr = env->cr[3] & ~0x1f;
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for (l1 = 0; l1 < 4; l1++) {
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cpu_physical_memory_read(pdp_addr + l1 * 8, (uint8_t *)&pdpe, 8);
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pdpe = le64_to_cpu(pdpe);
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if (pdpe & PG_PRESENT_MASK) {
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pd_addr = pdpe & 0x3fffffffff000ULL;
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for (l2 = 0; l2 < 512; l2++) {
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cpu_physical_memory_read(pd_addr + l2 * 8,
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(uint8_t *)&pde, 8);
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pde = le64_to_cpu(pde);
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if (pde & PG_PRESENT_MASK) {
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if (pde & PG_PSE_MASK) {
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/* 2M pages with PAE, CR4.PSE is ignored */
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print_pte(mon, (l1 << 30 ) + (l2 << 21), pde,
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~((target_phys_addr_t)(1 << 20) - 1));
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} else {
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pt_addr = pde & 0x3fffffffff000ULL;
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for (l3 = 0; l3 < 512; l3++) {
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cpu_physical_memory_read(pt_addr + l3 * 8,
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(uint8_t *)&pte, 8);
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pte = le64_to_cpu(pte);
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if (pte & PG_PRESENT_MASK) {
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print_pte(mon, (l1 << 30 ) + (l2 << 21)
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+ (l3 << 12),
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pte & ~PG_PSE_MASK,
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~(target_phys_addr_t)0xfff);
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}
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}
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}
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}
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}
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}
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}
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}
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#ifdef TARGET_X86_64
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static void tlb_info_64(Monitor *mon, CPUState *env)
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{
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uint64_t l1, l2, l3, l4;
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uint64_t pml4e, pdpe, pde, pte;
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uint64_t pml4_addr, pdp_addr, pd_addr, pt_addr;
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pml4_addr = env->cr[3] & 0x3fffffffff000ULL;
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for (l1 = 0; l1 < 512; l1++) {
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cpu_physical_memory_read(pml4_addr + l1 * 8, (uint8_t *)&pml4e, 8);
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pml4e = le64_to_cpu(pml4e);
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if (pml4e & PG_PRESENT_MASK) {
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pdp_addr = pml4e & 0x3fffffffff000ULL;
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for (l2 = 0; l2 < 512; l2++) {
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cpu_physical_memory_read(pdp_addr + l2 * 8, (uint8_t *)&pdpe,
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8);
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pdpe = le64_to_cpu(pdpe);
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if (pdpe & PG_PRESENT_MASK) {
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if (pdpe & PG_PSE_MASK) {
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/* 1G pages, CR4.PSE is ignored */
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print_pte(mon, (l1 << 39) + (l2 << 30), pdpe,
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0x3ffffc0000000ULL);
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} else {
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pd_addr = pdpe & 0x3fffffffff000ULL;
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for (l3 = 0; l3 < 512; l3++) {
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cpu_physical_memory_read(pd_addr + l3 * 8,
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(uint8_t *)&pde, 8);
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pde = le64_to_cpu(pde);
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if (pde & PG_PRESENT_MASK) {
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if (pde & PG_PSE_MASK) {
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/* 2M pages, CR4.PSE is ignored */
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print_pte(mon, (l1 << 39) + (l2 << 30) +
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(l3 << 21), pde,
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0x3ffffffe00000ULL);
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} else {
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pt_addr = pde & 0x3fffffffff000ULL;
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for (l4 = 0; l4 < 512; l4++) {
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cpu_physical_memory_read(pt_addr
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+ l4 * 8,
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(uint8_t *)&pte,
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8);
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pte = le64_to_cpu(pte);
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if (pte & PG_PRESENT_MASK) {
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print_pte(mon, (l1 << 39) +
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(l2 << 30) +
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(l3 << 21) + (l4 << 12),
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pte & ~PG_PSE_MASK,
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0x3fffffffff000ULL);
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}
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}
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}
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}
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}
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}
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}
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}
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}
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}
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}
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#endif
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static void tlb_info(Monitor *mon)
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{
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CPUState *env;
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env = mon_get_cpu();
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if (!(env->cr[0] & CR0_PG_MASK)) {
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monitor_printf(mon, "PG disabled\n");
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return;
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}
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if (env->cr[4] & CR4_PAE_MASK) {
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#ifdef TARGET_X86_64
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if (env->hflags & HF_LMA_MASK) {
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tlb_info_64(mon, env);
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} else
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#endif
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{
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tlb_info_pae32(mon, env);
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}
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} else {
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tlb_info_32(mon, env);
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}
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}
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static void mem_print(Monitor *mon, uint32_t *pstart, int *plast_prot,
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uint32_t end, int prot)
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{
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