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target-mips: add missing restriction in DAUI instruction

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rs cannot be the zero register, Reserved Instruction exception must be
signalled for this case.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Leon Alrae 2015-09-09 14:45:36 +01:00
parent 3adafef2f3
commit db77d85239
1 changed files with 3 additions and 1 deletions
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4
target-mips/translate.c
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@ -19525,7 +19525,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
/* OPC_DAUI */ /* OPC_DAUI */
check_mips_64(ctx); check_mips_64(ctx);
if (rt != 0) { if (rs == 0) {
generate_exception(ctx, EXCP_RI);
} else if (rt != 0) {
TCGv t0 = tcg_temp_new(); TCGv t0 = tcg_temp_new();
gen_load_gpr(t0, rs); gen_load_gpr(t0, rs);
tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16); tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16);