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target-arm: A64: fix TLB flush instructions

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According to the ARM ARM we weren't correctly flushing the TLB entries
where bits 63:56 didn't match bit 55 of the virtual address. This
exposed a problem when we switched QEMU's internal TARGET_PAGE_BITS to
12 for aarch64.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1406733627-24255-3-git-send-email-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alex Bennée 2014-08-04 14:41:56 +01:00 committed by Peter Maydell
parent dcd82c118c
commit dbb1fb277c
1 changed files with 8 additions and 2 deletions
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10
target-arm/helper.c
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@ -1801,12 +1801,17 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env,
return CP_ACCESS_OK; return CP_ACCESS_OK;
} }
/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
* Page D4-1736 (DDI0487A.b)
*/
static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
/* Invalidate by VA (AArch64 version) */ /* Invalidate by VA (AArch64 version) */
ARMCPU *cpu = arm_env_get_cpu(env); ARMCPU *cpu = arm_env_get_cpu(env);
uint64_t pageaddr = value << 12; uint64_t pageaddr = sextract64(value << 12, 0, 56);
tlb_flush_page(CPU(cpu), pageaddr); tlb_flush_page(CPU(cpu), pageaddr);
} }
@ -1815,7 +1820,8 @@ static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
{ {
/* Invalidate by VA, all ASIDs (AArch64 version) */ /* Invalidate by VA, all ASIDs (AArch64 version) */
ARMCPU *cpu = arm_env_get_cpu(env); ARMCPU *cpu = arm_env_get_cpu(env);
uint64_t pageaddr = value << 12; uint64_t pageaddr = sextract64(value << 12, 0, 56);
tlb_flush_page(CPU(cpu), pageaddr); tlb_flush_page(CPU(cpu), pageaddr);
} }