bcm2835_ic: add bcm2835 interrupt controller
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Andrew Baumann
Peter Maydell
parent
04f1ab15b9
commit
e3ece3e34d
@ -24,6 +24,7 @@ obj-$(CONFIG_GRLIB) += grlib_irqmp.o
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obj-$(CONFIG_IOAPIC) += ioapic.o
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obj-$(CONFIG_OMAP) += omap_intc.o
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obj-$(CONFIG_OPENPIC_KVM) += openpic_kvm.o
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obj-$(CONFIG_RASPI) += bcm2835_ic.o
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obj-$(CONFIG_SH4) += sh_intc.o
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obj-$(CONFIG_XICS) += xics.o
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obj-$(CONFIG_XICS_KVM) += xics_kvm.o
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236
hw/intc/bcm2835_ic.c
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236
hw/intc/bcm2835_ic.c
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@ -0,0 +1,236 @@
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/*
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* Raspberry Pi emulation (c) 2012 Gregory Estrade
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* Refactoring for Pi2 Copyright (c) 2015, Microsoft. Written by Andrew Baumann.
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* This code is licensed under the GNU GPLv2 and later.
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* Heavily based on pl190.c, copyright terms below:
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*
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* Arm PrimeCell PL190 Vector Interrupt Controller
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*
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* Copyright (c) 2006 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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#include "hw/intc/bcm2835_ic.h"
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#define GPU_IRQS 64
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#define ARM_IRQS 8
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#define IRQ_PENDING_BASIC 0x00 /* IRQ basic pending */
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#define IRQ_PENDING_1 0x04 /* IRQ pending 1 */
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#define IRQ_PENDING_2 0x08 /* IRQ pending 2 */
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#define FIQ_CONTROL 0x0C /* FIQ register */
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#define IRQ_ENABLE_1 0x10 /* Interrupt enable register 1 */
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#define IRQ_ENABLE_2 0x14 /* Interrupt enable register 2 */
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#define IRQ_ENABLE_BASIC 0x18 /* Base interrupt enable register */
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#define IRQ_DISABLE_1 0x1C /* Interrupt disable register 1 */
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#define IRQ_DISABLE_2 0x20 /* Interrupt disable register 2 */
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#define IRQ_DISABLE_BASIC 0x24 /* Base interrupt disable register */
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/* Update interrupts. */
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static void bcm2835_ic_update(BCM2835ICState *s)
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{
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bool set = false;
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if (s->fiq_enable) {
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if (s->fiq_select >= GPU_IRQS) {
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/* ARM IRQ */
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set = extract32(s->arm_irq_level, s->fiq_select - GPU_IRQS, 1);
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} else {
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set = extract64(s->gpu_irq_level, s->fiq_select, 1);
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}
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}
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qemu_set_irq(s->fiq, set);
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set = (s->gpu_irq_level & s->gpu_irq_enable)
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|| (s->arm_irq_level & s->arm_irq_enable);
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qemu_set_irq(s->irq, set);
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}
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static void bcm2835_ic_set_gpu_irq(void *opaque, int irq, int level)
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{
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BCM2835ICState *s = opaque;
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assert(irq >= 0 && irq < 64);
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s->gpu_irq_level = deposit64(s->gpu_irq_level, irq, 1, level != 0);
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bcm2835_ic_update(s);
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}
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static void bcm2835_ic_set_arm_irq(void *opaque, int irq, int level)
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{
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BCM2835ICState *s = opaque;
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assert(irq >= 0 && irq < 8);
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s->arm_irq_level = deposit32(s->arm_irq_level, irq, 1, level != 0);
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bcm2835_ic_update(s);
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}
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static const int irq_dups[] = { 7, 9, 10, 18, 19, 53, 54, 55, 56, 57, 62 };
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static uint64_t bcm2835_ic_read(void *opaque, hwaddr offset, unsigned size)
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{
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BCM2835ICState *s = opaque;
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uint32_t res = 0;
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uint64_t gpu_pending = s->gpu_irq_level & s->gpu_irq_enable;
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int i;
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switch (offset) {
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case IRQ_PENDING_BASIC:
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/* bits 0-7: ARM irqs */
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res = s->arm_irq_level & s->arm_irq_enable;
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/* bits 8 & 9: pending registers 1 & 2 */
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res |= (((uint32_t)gpu_pending) != 0) << 8;
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res |= ((gpu_pending >> 32) != 0) << 9;
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/* bits 10-20: selected GPU IRQs */
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for (i = 0; i < ARRAY_SIZE(irq_dups); i++) {
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res |= extract64(gpu_pending, irq_dups[i], 1) << (i + 10);
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}
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break;
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case IRQ_PENDING_1:
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res = gpu_pending;
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break;
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case IRQ_PENDING_2:
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res = gpu_pending >> 32;
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break;
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case FIQ_CONTROL:
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res = (s->fiq_enable << 7) | s->fiq_select;
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break;
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case IRQ_ENABLE_1:
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res = s->gpu_irq_enable;
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break;
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case IRQ_ENABLE_2:
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res = s->gpu_irq_enable >> 32;
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break;
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case IRQ_ENABLE_BASIC:
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res = s->arm_irq_enable;
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break;
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case IRQ_DISABLE_1:
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res = ~s->gpu_irq_enable;
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break;
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case IRQ_DISABLE_2:
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res = ~s->gpu_irq_enable >> 32;
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break;
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case IRQ_DISABLE_BASIC:
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res = ~s->arm_irq_enable;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
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__func__, offset);
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return 0;
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}
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return res;
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}
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static void bcm2835_ic_write(void *opaque, hwaddr offset, uint64_t val,
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unsigned size)
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{
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BCM2835ICState *s = opaque;
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switch (offset) {
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case FIQ_CONTROL:
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s->fiq_select = extract32(val, 0, 7);
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s->fiq_enable = extract32(val, 7, 1);
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break;
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case IRQ_ENABLE_1:
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s->gpu_irq_enable |= val;
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break;
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case IRQ_ENABLE_2:
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s->gpu_irq_enable |= val << 32;
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break;
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case IRQ_ENABLE_BASIC:
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s->arm_irq_enable |= val & 0xff;
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break;
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case IRQ_DISABLE_1:
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s->gpu_irq_enable &= ~val;
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break;
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case IRQ_DISABLE_2:
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s->gpu_irq_enable &= ~(val << 32);
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break;
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case IRQ_DISABLE_BASIC:
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s->arm_irq_enable &= ~val & 0xff;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
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__func__, offset);
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return;
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}
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bcm2835_ic_update(s);
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}
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static const MemoryRegionOps bcm2835_ic_ops = {
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.read = bcm2835_ic_read,
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.write = bcm2835_ic_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static void bcm2835_ic_reset(DeviceState *d)
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{
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BCM2835ICState *s = BCM2835_IC(d);
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s->gpu_irq_enable = 0;
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s->arm_irq_enable = 0;
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s->fiq_enable = false;
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s->fiq_select = 0;
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}
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static void bcm2835_ic_init(Object *obj)
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{
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BCM2835ICState *s = BCM2835_IC(obj);
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memory_region_init_io(&s->iomem, obj, &bcm2835_ic_ops, s, TYPE_BCM2835_IC,
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0x200);
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sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
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qdev_init_gpio_in_named(DEVICE(s), bcm2835_ic_set_gpu_irq,
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BCM2835_IC_GPU_IRQ, GPU_IRQS);
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qdev_init_gpio_in_named(DEVICE(s), bcm2835_ic_set_arm_irq,
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BCM2835_IC_ARM_IRQ, ARM_IRQS);
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sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
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sysbus_init_irq(SYS_BUS_DEVICE(s), &s->fiq);
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}
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static const VMStateDescription vmstate_bcm2835_ic = {
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.name = TYPE_BCM2835_IC,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(gpu_irq_level, BCM2835ICState),
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VMSTATE_UINT64(gpu_irq_enable, BCM2835ICState),
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VMSTATE_UINT8(arm_irq_level, BCM2835ICState),
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VMSTATE_UINT8(arm_irq_enable, BCM2835ICState),
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VMSTATE_BOOL(fiq_enable, BCM2835ICState),
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VMSTATE_UINT8(fiq_select, BCM2835ICState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void bcm2835_ic_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = bcm2835_ic_reset;
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dc->vmsd = &vmstate_bcm2835_ic;
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}
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static TypeInfo bcm2835_ic_info = {
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.name = TYPE_BCM2835_IC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(BCM2835ICState),
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.class_init = bcm2835_ic_class_init,
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.instance_init = bcm2835_ic_init,
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};
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static void bcm2835_ic_register_types(void)
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{
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type_register_static(&bcm2835_ic_info);
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}
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type_init(bcm2835_ic_register_types)
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33
include/hw/intc/bcm2835_ic.h
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33
include/hw/intc/bcm2835_ic.h
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@ -0,0 +1,33 @@
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/*
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* Raspberry Pi emulation (c) 2012 Gregory Estrade
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* This code is licensed under the GNU GPLv2 and later.
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*/
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#ifndef BCM2835_IC_H
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#define BCM2835_IC_H
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#include "hw/sysbus.h"
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#define TYPE_BCM2835_IC "bcm2835-ic"
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#define BCM2835_IC(obj) OBJECT_CHECK(BCM2835ICState, (obj), TYPE_BCM2835_IC)
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#define BCM2835_IC_GPU_IRQ "gpu-irq"
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#define BCM2835_IC_ARM_IRQ "arm-irq"
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typedef struct BCM2835ICState {
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/*< private >*/
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SysBusDevice busdev;
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/*< public >*/
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MemoryRegion iomem;
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qemu_irq irq;
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qemu_irq fiq;
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/* 64 GPU IRQs + 8 ARM IRQs = 72 total (GPU first) */
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uint64_t gpu_irq_level, gpu_irq_enable;
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uint8_t arm_irq_level, arm_irq_enable;
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bool fiq_enable;
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uint8_t fiq_select;
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} BCM2835ICState;
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#endif
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