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target/arm: Make MPU_CTRL register banked for v8M

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Make the MPU_CTRL register banked if v8M security extensions are
enabled.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-16-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2017-09-07 13:54:53 +01:00
parent 1bc04a8880
commit ecf5e8eae8
4 changed files with 11 additions and 8 deletions
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9
hw/intc/armv7m_nvic.c
View File

@ -541,7 +541,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
return cpu->pmsav7_dregion << 8; return cpu->pmsav7_dregion << 8;
break; break;
case 0xd94: /* MPU_CTRL */ case 0xd94: /* MPU_CTRL */
return cpu->env.v7m.mpu_ctrl; return cpu->env.v7m.mpu_ctrl[attrs.secure];
case 0xd98: /* MPU_RNR */ case 0xd98: /* MPU_RNR */
return cpu->env.pmsav7.rnr[attrs.secure]; return cpu->env.pmsav7.rnr[attrs.secure];
case 0xd9c: /* MPU_RBAR */ case 0xd9c: /* MPU_RBAR */
@ -720,9 +720,10 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
qemu_log_mask(LOG_GUEST_ERROR, "MPU_CTRL: HFNMIENA and !ENABLE is " qemu_log_mask(LOG_GUEST_ERROR, "MPU_CTRL: HFNMIENA and !ENABLE is "
"UNPREDICTABLE\n"); "UNPREDICTABLE\n");
} }
cpu->env.v7m.mpu_ctrl = value & (R_V7M_MPU_CTRL_ENABLE_MASK | cpu->env.v7m.mpu_ctrl[attrs.secure]
R_V7M_MPU_CTRL_HFNMIENA_MASK | = value & (R_V7M_MPU_CTRL_ENABLE_MASK |
R_V7M_MPU_CTRL_PRIVDEFENA_MASK); R_V7M_MPU_CTRL_HFNMIENA_MASK |
R_V7M_MPU_CTRL_PRIVDEFENA_MASK);
tlb_flush(CPU(cpu)); tlb_flush(CPU(cpu));
break; break;
case 0xd98: /* MPU_RNR */ case 0xd98: /* MPU_RNR */

2
target/arm/cpu.h
View File

@ -429,7 +429,7 @@ typedef struct CPUARMState {
uint32_t dfsr; /* Debug Fault Status Register */ uint32_t dfsr; /* Debug Fault Status Register */
uint32_t mmfar; /* MemManage Fault Address */ uint32_t mmfar; /* MemManage Fault Address */
uint32_t bfar; /* BusFault Address */ uint32_t bfar; /* BusFault Address */
unsigned mpu_ctrl; /* MPU_CTRL */ unsigned mpu_ctrl[2]; /* MPU_CTRL */
int exception; int exception;
uint32_t primask[2]; uint32_t primask[2];
uint32_t faultmask[2]; uint32_t faultmask[2];

5
target/arm/helper.c
View File

@ -7091,7 +7091,7 @@ static inline bool regime_translation_disabled(CPUARMState *env,
ARMMMUIdx mmu_idx) ARMMMUIdx mmu_idx)
{ {
if (arm_feature(env, ARM_FEATURE_M)) { if (arm_feature(env, ARM_FEATURE_M)) {
switch (env->v7m.mpu_ctrl & switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] &
(R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) {
case R_V7M_MPU_CTRL_ENABLE_MASK: case R_V7M_MPU_CTRL_ENABLE_MASK:
/* Enabled, but not for HardFault and NMI */ /* Enabled, but not for HardFault and NMI */
@ -8251,7 +8251,8 @@ static bool pmsav7_use_background_region(ARMCPU *cpu,
} }
if (arm_feature(env, ARM_FEATURE_M)) { if (arm_feature(env, ARM_FEATURE_M)) {
return env->v7m.mpu_ctrl & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)]
& R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
} else { } else {
return regime_sctlr(env, mmu_idx) & SCTLR_BR; return regime_sctlr(env, mmu_idx) & SCTLR_BR;
} }

3
target/arm/machine.c
View File

@ -123,7 +123,7 @@ static const VMStateDescription vmstate_m = {
VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), VMSTATE_UINT32(env.v7m.dfsr, ARMCPU),
VMSTATE_UINT32(env.v7m.mmfar, ARMCPU), VMSTATE_UINT32(env.v7m.mmfar, ARMCPU),
VMSTATE_UINT32(env.v7m.bfar, ARMCPU), VMSTATE_UINT32(env.v7m.bfar, ARMCPU),
VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU), VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU),
VMSTATE_INT32(env.v7m.exception, ARMCPU), VMSTATE_INT32(env.v7m.exception, ARMCPU),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
}, },
@ -270,6 +270,7 @@ static const VMStateDescription vmstate_m_security = {
0, vmstate_info_uint32, uint32_t), 0, vmstate_info_uint32, uint32_t),
VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU),
VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate),
VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
}; };