CRIS MMU Updates
* Add support for exec faults and for the k protection bit. * Abort if search_pc causes recursive mmu faults. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4349 c046a42c-6fe2-441c-8c8c-71466251a162
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				@ -79,6 +79,12 @@ int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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	miss = cris_mmu_translate(&res, env, address, rw, mmu_idx);
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						miss = cris_mmu_translate(&res, env, address, rw, mmu_idx);
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	if (miss)
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						if (miss)
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	{
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						{
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							if (env->exception_index == EXCP_MMU_FAULT)
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								cpu_abort(env, 
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									  "CRIS: Illegal recursive bus fault."
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									  "addr=%x rw=%d\n",
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									  address, rw);
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		env->exception_index = EXCP_MMU_FAULT;
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							env->exception_index = EXCP_MMU_FAULT;
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		env->fault_vector = res.bf_vec;
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							env->fault_vector = res.bf_vec;
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		r = 1;
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							r = 1;
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@ -101,7 +107,7 @@ void do_interrupt(CPUState *env)
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{
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					{
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	int ex_vec = -1;
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						int ex_vec = -1;
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	D(fprintf (stderr, "exception index=%d interrupt_req=%d\n",
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						D(fprintf (logfile, "exception index=%d interrupt_req=%d\n",
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		   env->exception_index,
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							   env->exception_index,
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		   env->interrupt_request));
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							   env->interrupt_request));
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@ -133,8 +139,9 @@ void do_interrupt(CPUState *env)
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	}
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						}
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	if ((env->pregs[PR_CCS] & U_FLAG)) {
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						if ((env->pregs[PR_CCS] & U_FLAG)) {
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		D(fprintf(logfile, "excp isr=%x PC=%x ERP=%x pid=%x ccs=%x cc=%d %x\n",
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							D(fprintf(logfile, "excp isr=%x PC=%x SP=%x ERP=%x pid=%x ccs=%x cc=%d %x\n",
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			  ex_vec, env->pc,
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								  ex_vec, env->pc,
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								  env->regs[R_SP],
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			  env->pregs[PR_ERP], env->pregs[PR_PID],
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								  env->pregs[PR_ERP], env->pregs[PR_PID],
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			  env->pregs[PR_CCS],
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								  env->pregs[PR_CCS],
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			  env->cc_op, env->cc_mask));
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								  env->cc_op, env->cc_mask));
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@ -32,12 +32,12 @@
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#define D(x)
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					#define D(x)
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static int cris_mmu_enabled(uint32_t rw_gc_cfg)
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					static inline int cris_mmu_enabled(uint32_t rw_gc_cfg)
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{
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					{
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	return (rw_gc_cfg & 12) != 0;
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						return (rw_gc_cfg & 12) != 0;
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}
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					}
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static int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
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					static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
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{
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					{
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	return (1 << seg) & rw_mm_cfg;
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						return (1 << seg) & rw_mm_cfg;
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}
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					}
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@ -187,15 +187,26 @@ static int cris_mmu_translate_page(struct cris_mmu_result_t *res,
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		set_exception_vector(0x0a, d_mmu_access);
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							set_exception_vector(0x0a, d_mmu_access);
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		set_exception_vector(0x0b, d_mmu_write);
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							set_exception_vector(0x0b, d_mmu_write);
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		*/
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							*/
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		if (!tlb_g 
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							if (!tlb_g
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		    && tlb_pid != (env->pregs[PR_PID] & 0xff)) {
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							    && tlb_pid != (env->pregs[PR_PID] & 0xff)) {
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			D(printf ("tlb: wrong pid %x %x pc=%x\n", 
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								D(printf ("tlb: wrong pid %x %x pc=%x\n", 
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				 tlb_pid, env->pregs[PR_PID], env->pc));
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									 tlb_pid, env->pregs[PR_PID], env->pc));
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			match = 0;
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								match = 0;
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			res->bf_vec = vect_base;
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								res->bf_vec = vect_base;
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							} else if (cfg_k && tlb_k && usermode) {
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								D(printf ("tlb: kernel protected %x lo=%x pc=%x\n", 
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									  vaddr, lo, env->pc));
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								match = 0;
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								res->bf_vec = vect_base + 2;
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		} else if (rw == 1 && cfg_w && !tlb_w) {
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							} else if (rw == 1 && cfg_w && !tlb_w) {
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			D(printf ("tlb: write protected %x lo=%x\n", 
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								D(printf ("tlb: write protected %x lo=%x pc=%x\n", 
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				vaddr, lo));
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									  vaddr, lo, env->pc));
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								match = 0;
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								/* write accesses never go through the I mmu.  */
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								res->bf_vec = vect_base + 3;
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							} else if (rw == 2 && cfg_x && !tlb_x) {
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								D(printf ("tlb: exec protected %x lo=%x pc=%x\n", 
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									 vaddr, lo, env->pc));
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			match = 0;
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								match = 0;
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			res->bf_vec = vect_base + 3;
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								res->bf_vec = vect_base + 3;
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		} else if (cfg_v && !tlb_v) {
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							} else if (cfg_v && !tlb_v) {
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@ -60,8 +60,8 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
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    saved_env = env;
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					    saved_env = env;
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    env = cpu_single_env;
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					    env = cpu_single_env;
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    D(fprintf(logfile, "%s ra=%x acr=%x %x\n", __func__, retaddr,
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					    D(fprintf(logfile, "%s pc=%x tpc=%x ra=%x\n", __func__, 
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	    env->regs[R_ACR], saved_env->regs[R_ACR]));
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						     env->pc, env->debug1, retaddr));
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    ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
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					    ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
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    if (__builtin_expect(ret, 0)) {
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					    if (__builtin_expect(ret, 0)) {
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        if (retaddr) {
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					        if (retaddr) {
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@ -89,7 +89,7 @@ void helper_tlb_update(uint32_t T0)
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		return;
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							return;
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	vaddr = cris_mmu_tlb_latest_update(env, T0);
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						vaddr = cris_mmu_tlb_latest_update(env, T0);
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	D(printf("flush old_vaddr=%x vaddr=%x T0=%x\n", vaddr, 
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						D(fprintf(logfile, "flush old_vaddr=%x vaddr=%x T0=%x\n", vaddr, 
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		 env->sregs[SFR_R_MM_CAUSE] & TARGET_PAGE_MASK, T0));
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							 env->sregs[SFR_R_MM_CAUSE] & TARGET_PAGE_MASK, T0));
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	tlb_flush_page(env, vaddr);
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						tlb_flush_page(env, vaddr);
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#endif
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					#endif
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