david.venhoff/QEMU-Nyx-fork
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

pcie_aer: support configurable AER capa version

Browse Source 
Now, AER capa version is fixed to v2, if assigned device isn't v2,
then this value will be inconsistent between guest and host

Signed-off-by: Dou Liyang <douly.fnst@cn.fujitsu.com>
Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Dou Liyang 2016-12-21 16:21:31 +08:00 committed by Michael S. Tsirkin
parent 33848ceed7
commit f18c697b55
6 changed files with 13 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
hw/net/e1000e.c
View File

@ -472,7 +472,8 @@ static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp)
hw_error("Failed to initialize PM capability");
}
if (pcie_aer_init(pci_dev, e1000e_aer_offset, PCI_ERR_SIZEOF, NULL) < 0) {
if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset,
PCI_ERR_SIZEOF, NULL) < 0) {
hw_error("Failed to initialize AER capability");
}

3
hw/pci-bridge/ioh3420.c
View File

@ -135,7 +135,8 @@ static int ioh3420_initfn(PCIDevice *d)
goto err_pcie_cap;
}
rc = pcie_aer_init(d, IOH_EP_AER_OFFSET, PCI_ERR_SIZEOF, &err);
rc = pcie_aer_init(d, PCI_ERR_VER, IOH_EP_AER_OFFSET,
PCI_ERR_SIZEOF, &err);
if (rc < 0) {
error_report_err(err);
goto err;

3
hw/pci-bridge/xio3130_downstream.c
View File

@ -97,7 +97,8 @@ static int xio3130_downstream_initfn(PCIDevice *d)
goto err_pcie_cap;
}
rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF, &err);
rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,
PCI_ERR_SIZEOF, &err);
if (rc < 0) {
error_report_err(err);
goto err;

3
hw/pci-bridge/xio3130_upstream.c
View File

@ -85,7 +85,8 @@ static int xio3130_upstream_initfn(PCIDevice *d)
pcie_cap_flr_init(d);
pcie_cap_deverr_init(d);
rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF, &err);
rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,
PCI_ERR_SIZEOF, &err);
if (rc < 0) {
error_report_err(err);
goto err;

6
hw/pci/pcie_aer.c
View File

@ -97,10 +97,10 @@ static void aer_log_clear_all_err(PCIEAERLog *aer_log)
aer_log->log_num = 0;
}
int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size,
Error **errp)
int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset,
uint16_t size, Error **errp)
{
pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, PCI_ERR_VER,
pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, cap_ver,
offset, size);
dev->exp.aer_cap = offset;

4
include/hw/pci/pcie_aer.h
View File

@ -86,8 +86,8 @@ struct PCIEAERErr {
extern const VMStateDescription vmstate_pcie_aer_log;
int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size,
Error **errp);
int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset,
uint16_t size, Error **errp);
void pcie_aer_exit(PCIDevice *dev);
void pcie_aer_write_config(PCIDevice *dev,
uint32_t addr, uint32_t val, int len);