PPC: Fix compilation with TCG debug
The recent VSX patches broken compilation of QEMU when configurated with --enable-debug, as it was treating "target long" TCG variables as "i64" which is not true for 32bit targets. This patch fixes all the places that the compiler has found to use the correct variable type and if necessary manually cast. Reported-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Alexander Graf
Aurelien Jarno
parent
e8092f7ae1
commit
f976b09ea2
@ -2567,6 +2567,14 @@ static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
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}
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}
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static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
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{
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TCGv tmp = tcg_temp_new();
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gen_qemu_ld32u(ctx, tmp, addr);
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tcg_gen_extu_tl_i64(val, tmp);
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tcg_temp_free(tmp);
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}
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static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
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{
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if (unlikely(ctx->le_mode)) {
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@ -2616,6 +2624,14 @@ static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
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}
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}
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static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
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{
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TCGv tmp = tcg_temp_new();
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tcg_gen_trunc_i64_tl(tmp, val);
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gen_qemu_st32(ctx, tmp, addr);
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tcg_temp_free(tmp);
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}
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static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
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{
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if (unlikely(ctx->le_mode)) {
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@ -7048,13 +7064,14 @@ static void gen_lxvdsx(DisasContext *ctx)
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EA = tcg_temp_new();
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gen_addr_reg_index(ctx, EA);
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gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
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tcg_gen_mov_tl(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
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tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
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tcg_temp_free(EA);
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}
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static void gen_lxvw4x(DisasContext *ctx)
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{
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TCGv EA, tmp;
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TCGv EA;
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TCGv_i64 tmp;
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TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
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TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
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if (unlikely(!ctx->vsx_enabled)) {
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@ -7063,21 +7080,22 @@ static void gen_lxvw4x(DisasContext *ctx)
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}
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gen_set_access_type(ctx, ACCESS_INT);
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EA = tcg_temp_new();
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tmp = tcg_temp_new();
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tmp = tcg_temp_new_i64();
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gen_addr_reg_index(ctx, EA);
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gen_qemu_ld32u(ctx, tmp, EA);
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gen_qemu_ld32u_i64(ctx, tmp, EA);
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tcg_gen_addi_tl(EA, EA, 4);
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gen_qemu_ld32u(ctx, xth, EA);
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gen_qemu_ld32u_i64(ctx, xth, EA);
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tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
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tcg_gen_addi_tl(EA, EA, 4);
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gen_qemu_ld32u(ctx, tmp, EA);
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gen_qemu_ld32u_i64(ctx, tmp, EA);
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tcg_gen_addi_tl(EA, EA, 4);
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gen_qemu_ld32u(ctx, xtl, EA);
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gen_qemu_ld32u_i64(ctx, xtl, EA);
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tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
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tcg_temp_free(EA);
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tcg_temp_free(tmp);
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tcg_temp_free_i64(tmp);
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}
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static void gen_stxsdx(DisasContext *ctx)
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@ -7112,7 +7130,8 @@ static void gen_stxvd2x(DisasContext *ctx)
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static void gen_stxvw4x(DisasContext *ctx)
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{
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TCGv EA, tmp;
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TCGv_i64 tmp;
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TCGv EA;
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if (unlikely(!ctx->vsx_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_VSXU);
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return;
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@ -7120,21 +7139,21 @@ static void gen_stxvw4x(DisasContext *ctx)
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gen_set_access_type(ctx, ACCESS_INT);
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EA = tcg_temp_new();
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gen_addr_reg_index(ctx, EA);
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tmp = tcg_temp_new();
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tmp = tcg_temp_new_i64();
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tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
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gen_qemu_st32(ctx, tmp, EA);
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gen_qemu_st32_i64(ctx, tmp, EA);
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tcg_gen_addi_tl(EA, EA, 4);
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gen_qemu_st32(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
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gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
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tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
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tcg_gen_addi_tl(EA, EA, 4);
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gen_qemu_st32(ctx, tmp, EA);
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gen_qemu_st32_i64(ctx, tmp, EA);
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tcg_gen_addi_tl(EA, EA, 4);
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gen_qemu_st32(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
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gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
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tcg_temp_free(EA);
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tcg_temp_free(tmp);
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tcg_temp_free_i64(tmp);
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}
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static void gen_xxpermdi(DisasContext *ctx)
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@ -7171,8 +7190,8 @@ static void glue(gen_, name)(DisasContext * ctx) \
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gen_exception(ctx, POWERPC_EXCP_VSXU); \
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return; \
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} \
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xb = tcg_temp_new(); \
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sgm = tcg_temp_new(); \
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xb = tcg_temp_new_i64(); \
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sgm = tcg_temp_new_i64(); \
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tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
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tcg_gen_movi_i64(sgm, sgn_mask); \
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switch (op) { \
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@ -7189,18 +7208,18 @@ static void glue(gen_, name)(DisasContext * ctx) \
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break; \
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} \
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case OP_CPSGN: { \
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TCGv_i64 xa = tcg_temp_new(); \
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TCGv_i64 xa = tcg_temp_new_i64(); \
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tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
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tcg_gen_and_i64(xa, xa, sgm); \
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tcg_gen_andc_i64(xb, xb, sgm); \
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tcg_gen_or_i64(xb, xb, xa); \
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tcg_temp_free(xa); \
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tcg_temp_free_i64(xa); \
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break; \
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} \
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} \
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tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
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tcg_temp_free(xb); \
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tcg_temp_free(sgm); \
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tcg_temp_free_i64(xb); \
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tcg_temp_free_i64(sgm); \
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}
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VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
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@ -7216,9 +7235,9 @@ static void glue(gen_, name)(DisasContext * ctx) \
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gen_exception(ctx, POWERPC_EXCP_VSXU); \
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return; \
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} \
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xbh = tcg_temp_new(); \
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xbl = tcg_temp_new(); \
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sgm = tcg_temp_new(); \
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xbh = tcg_temp_new_i64(); \
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xbl = tcg_temp_new_i64(); \
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sgm = tcg_temp_new_i64(); \
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tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
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tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
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tcg_gen_movi_i64(sgm, sgn_mask); \
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@ -7239,8 +7258,8 @@ static void glue(gen_, name)(DisasContext * ctx) \
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break; \
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} \
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case OP_CPSGN: { \
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TCGv_i64 xah = tcg_temp_new(); \
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TCGv_i64 xal = tcg_temp_new(); \
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TCGv_i64 xah = tcg_temp_new_i64(); \
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TCGv_i64 xal = tcg_temp_new_i64(); \
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tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
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tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
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tcg_gen_and_i64(xah, xah, sgm); \
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@ -7249,16 +7268,16 @@ static void glue(gen_, name)(DisasContext * ctx) \
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tcg_gen_andc_i64(xbl, xbl, sgm); \
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tcg_gen_or_i64(xbh, xbh, xah); \
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tcg_gen_or_i64(xbl, xbl, xal); \
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tcg_temp_free(xah); \
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tcg_temp_free(xal); \
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tcg_temp_free_i64(xah); \
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tcg_temp_free_i64(xal); \
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break; \
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} \
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} \
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tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
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tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
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tcg_temp_free(xbh); \
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tcg_temp_free(xbl); \
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tcg_temp_free(sgm); \
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tcg_temp_free_i64(xbh); \
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tcg_temp_free_i64(xbl); \
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tcg_temp_free_i64(sgm); \
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}
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VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
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@ -7284,11 +7303,11 @@ static void glue(gen_, name)(DisasContext * ctx) \
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cpu_vsrl(xB(ctx->opcode))); \
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}
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VSX_LOGICAL(xxland, tcg_gen_and_tl)
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VSX_LOGICAL(xxlandc, tcg_gen_andc_tl)
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VSX_LOGICAL(xxlor, tcg_gen_or_tl)
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VSX_LOGICAL(xxlxor, tcg_gen_xor_tl)
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VSX_LOGICAL(xxlnor, tcg_gen_nor_tl)
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VSX_LOGICAL(xxland, tcg_gen_and_i64)
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VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
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VSX_LOGICAL(xxlor, tcg_gen_or_i64)
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VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
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VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
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#define VSX_XXMRG(name, high) \
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static void glue(gen_, name)(DisasContext * ctx) \
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@ -7298,10 +7317,10 @@ static void glue(gen_, name)(DisasContext * ctx) \
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gen_exception(ctx, POWERPC_EXCP_VSXU); \
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return; \
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} \
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a0 = tcg_temp_new(); \
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a1 = tcg_temp_new(); \
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b0 = tcg_temp_new(); \
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b1 = tcg_temp_new(); \
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a0 = tcg_temp_new_i64(); \
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a1 = tcg_temp_new_i64(); \
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b0 = tcg_temp_new_i64(); \
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b1 = tcg_temp_new_i64(); \
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if (high) { \
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tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
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tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
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@ -7319,10 +7338,10 @@ static void glue(gen_, name)(DisasContext * ctx) \
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b0, a0, 32, 32); \
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tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
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b1, a1, 32, 32); \
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tcg_temp_free(a0); \
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tcg_temp_free(a1); \
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tcg_temp_free(b0); \
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tcg_temp_free(b1); \
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tcg_temp_free_i64(a0); \
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tcg_temp_free_i64(a1); \
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tcg_temp_free_i64(b0); \
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tcg_temp_free_i64(b1); \
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}
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VSX_XXMRG(xxmrghw, 1)
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@ -7335,9 +7354,9 @@ static void gen_xxsel(DisasContext * ctx)
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gen_exception(ctx, POWERPC_EXCP_VSXU);
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return;
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}
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a = tcg_temp_new();
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b = tcg_temp_new();
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c = tcg_temp_new();
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a = tcg_temp_new_i64();
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b = tcg_temp_new_i64();
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c = tcg_temp_new_i64();
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tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
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tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
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@ -7355,9 +7374,9 @@ static void gen_xxsel(DisasContext * ctx)
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tcg_gen_andc_i64(a, a, c);
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tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
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tcg_temp_free(a);
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tcg_temp_free(b);
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tcg_temp_free(c);
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tcg_temp_free_i64(a);
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tcg_temp_free_i64(b);
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tcg_temp_free_i64(c);
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}
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static void gen_xxspltw(DisasContext *ctx)
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@ -7372,8 +7391,8 @@ static void gen_xxspltw(DisasContext *ctx)
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return;
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}
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b = tcg_temp_new();
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b2 = tcg_temp_new();
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b = tcg_temp_new_i64();
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b2 = tcg_temp_new_i64();
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if (UIM(ctx->opcode) & 1) {
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tcg_gen_ext32u_i64(b, vsr);
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@ -7385,8 +7404,8 @@ static void gen_xxspltw(DisasContext *ctx)
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tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
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tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
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tcg_temp_free(b);
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tcg_temp_free(b2);
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tcg_temp_free_i64(b);
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tcg_temp_free_i64(b2);
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}
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static void gen_xxsldwi(DisasContext *ctx)
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@ -7396,8 +7415,8 @@ static void gen_xxsldwi(DisasContext *ctx)
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gen_exception(ctx, POWERPC_EXCP_VSXU);
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return;
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}
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xth = tcg_temp_new();
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xtl = tcg_temp_new();
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xth = tcg_temp_new_i64();
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xtl = tcg_temp_new_i64();
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switch (SHW(ctx->opcode)) {
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case 0: {
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@ -7406,7 +7425,7 @@ static void gen_xxsldwi(DisasContext *ctx)
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break;
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}
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case 1: {
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TCGv_i64 t0 = tcg_temp_new();
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TCGv_i64 t0 = tcg_temp_new_i64();
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tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
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tcg_gen_shli_i64(xth, xth, 32);
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tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
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@ -7417,7 +7436,7 @@ static void gen_xxsldwi(DisasContext *ctx)
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tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
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tcg_gen_shri_i64(t0, t0, 32);
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tcg_gen_or_i64(xtl, xtl, t0);
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tcg_temp_free(t0);
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tcg_temp_free_i64(t0);
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break;
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}
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case 2: {
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@ -7426,7 +7445,7 @@ static void gen_xxsldwi(DisasContext *ctx)
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break;
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}
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case 3: {
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TCGv_i64 t0 = tcg_temp_new();
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TCGv_i64 t0 = tcg_temp_new_i64();
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tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
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tcg_gen_shli_i64(xth, xth, 32);
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tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
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@ -7437,7 +7456,7 @@ static void gen_xxsldwi(DisasContext *ctx)
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tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
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tcg_gen_shri_i64(t0, t0, 32);
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tcg_gen_or_i64(xtl, xtl, t0);
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tcg_temp_free(t0);
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tcg_temp_free_i64(t0);
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break;
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}
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}
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@ -7445,8 +7464,8 @@ static void gen_xxsldwi(DisasContext *ctx)
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tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
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tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
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tcg_temp_free(xth);
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tcg_temp_free(xtl);
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tcg_temp_free_i64(xth);
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tcg_temp_free_i64(xtl);
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}
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