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Merge remote-tracking branch 'agraf/ppc-for-upstream' into staging

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# By Andreas Färber (2) and Alexander Graf (1)
# Via Alexander Graf
* agraf/ppc-for-upstream:
  target-ppc: Fix build for PPC_DEBUG_DISAS
  target-ppc: Fix unused variable warning for FLUSH_ALL_TLBS
  PPC: Unify dcbzl code path
This commit is contained in:
Anthony Liguori 2013-02-01 09:02:09 -06:00
commit fabb60424d
6 changed files with 35 additions and 43 deletions
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6
target-ppc/cpu.h
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@ -1857,10 +1857,8 @@ enum {
PPC_CACHE = 0x0000000200000000ULL, PPC_CACHE = 0x0000000200000000ULL,
/* icbi instruction */ /* icbi instruction */
PPC_CACHE_ICBI = 0x0000000400000000ULL, PPC_CACHE_ICBI = 0x0000000400000000ULL,
/* dcbz instruction with fixed cache line size */ /* dcbz instruction */
PPC_CACHE_DCBZ = 0x0000000800000000ULL, PPC_CACHE_DCBZ = 0x0000000800000000ULL,
/* dcbz instruction with tunable cache line size */
PPC_CACHE_DCBZT = 0x0000001000000000ULL,
/* dcba instruction */ /* dcba instruction */
PPC_CACHE_DCBA = 0x0000002000000000ULL, PPC_CACHE_DCBA = 0x0000002000000000ULL,
/* Freescale cache locking instructions */ /* Freescale cache locking instructions */
@ -1928,7 +1926,7 @@ enum {
| PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \ | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
| PPC_MEM_SYNC | PPC_MEM_EIEIO \ | PPC_MEM_SYNC | PPC_MEM_EIEIO \
| PPC_CACHE | PPC_CACHE_ICBI \ | PPC_CACHE | PPC_CACHE_ICBI \
| PPC_CACHE_DCBZ | PPC_CACHE_DCBZT \ | PPC_CACHE_DCBZ \
| PPC_CACHE_DCBA | PPC_CACHE_LOCK \ | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
| PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \ | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
| PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \ | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \

3
target-ppc/helper.h
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@ -25,8 +25,7 @@ DEF_HELPER_3(stmw, void, env, tl, i32)
DEF_HELPER_4(lsw, void, env, tl, i32, i32) DEF_HELPER_4(lsw, void, env, tl, i32, i32)
DEF_HELPER_5(lswx, void, env, tl, i32, i32, i32) DEF_HELPER_5(lswx, void, env, tl, i32, i32, i32)
DEF_HELPER_4(stsw, void, env, tl, i32, i32) DEF_HELPER_4(stsw, void, env, tl, i32, i32)
DEF_HELPER_2(dcbz, void, env, tl) DEF_HELPER_3(dcbz, void, env, tl, i32)
DEF_HELPER_2(dcbz_970, void, env, tl)
DEF_HELPER_2(icbi, void, env, tl) DEF_HELPER_2(icbi, void, env, tl)
DEF_HELPER_5(lscbx, tl, env, tl, i32, i32, i32) DEF_HELPER_5(lscbx, tl, env, tl, i32, i32, i32)

21
target-ppc/mem_helper.c
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@ -136,18 +136,21 @@ static void do_dcbz(CPUPPCState *env, target_ulong addr, int dcache_line_size)
} }
} }
void helper_dcbz(CPUPPCState *env, target_ulong addr) void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t is_dcbzl)
{ {
do_dcbz(env, addr, env->dcache_line_size); int dcbz_size = env->dcache_line_size;
}
void helper_dcbz_970(CPUPPCState *env, target_ulong addr) #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
{ if (!is_dcbzl &&
if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) { (env->excp_model == POWERPC_EXCP_970) &&
do_dcbz(env, addr, 32); ((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) {
} else { dcbz_size = 32;
do_dcbz(env, addr, env->dcache_line_size);
} }
#endif
/* XXX add e500mc support */
do_dcbz(env, addr, dcbz_size);
} }
void helper_icbi(CPUPPCState *env, target_ulong addr) void helper_icbi(CPUPPCState *env, target_ulong addr)

3
target-ppc/mmu_helper.c
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@ -2260,8 +2260,9 @@ void helper_store_601_batu(CPUPPCState *env, uint32_t nr, target_ulong value)
void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value) void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value)
{ {
#if !defined(FLUSH_ALL_TLBS)
target_ulong mask; target_ulong mask;
#if defined(FLUSH_ALL_TLBS) #else
int do_inval; int do_inval;
#endif #endif

35
target-ppc/translate.c
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@ -4118,29 +4118,21 @@ static void gen_dcbtst(DisasContext *ctx)
/* dcbz */ /* dcbz */
static void gen_dcbz(DisasContext *ctx) static void gen_dcbz(DisasContext *ctx)
{ {
TCGv t0; TCGv tcgv_addr;
gen_set_access_type(ctx, ACCESS_CACHE); TCGv_i32 tcgv_is_dcbzl;
/* NIP cannot be restored if the memory exception comes from an helper */ int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
gen_update_nip(ctx, ctx->nip - 4);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
gen_helper_dcbz(cpu_env, t0);
tcg_temp_free(t0);
}
static void gen_dcbz_970(DisasContext *ctx)
{
TCGv t0;
gen_set_access_type(ctx, ACCESS_CACHE); gen_set_access_type(ctx, ACCESS_CACHE);
/* NIP cannot be restored if the memory exception comes from an helper */ /* NIP cannot be restored if the memory exception comes from an helper */
gen_update_nip(ctx, ctx->nip - 4); gen_update_nip(ctx, ctx->nip - 4);
t0 = tcg_temp_new(); tcgv_addr = tcg_temp_new();
gen_addr_reg_index(ctx, t0); tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
if (ctx->opcode & 0x00200000)
gen_helper_dcbz(cpu_env, t0); gen_addr_reg_index(ctx, tcgv_addr);
else gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
gen_helper_dcbz_970(cpu_env, t0);
tcg_temp_free(t0); tcg_temp_free(tcgv_addr);
tcg_temp_free_i32(tcgv_is_dcbzl);
} }
/* dst / dstt */ /* dst / dstt */
@ -8648,8 +8640,7 @@ GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE), GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE), GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ), GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT),
GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
@ -9698,7 +9689,7 @@ static inline void gen_intermediate_code_internal(CPUPPCState *env,
} }
LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n", LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
opc3(ctx.opcode), little_endian ? "little" : "big"); opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(ctx.nip); tcg_gen_debug_insn_start(ctx.nip);
} }

10
target-ppc/translate_init.c
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@ -6298,7 +6298,7 @@ static void init_proc_7457 (CPUPPCState *env)
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
PPC_FLOAT_STFIWX | \ PPC_FLOAT_STFIWX | \
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_64B | PPC_ALTIVEC | \ PPC_64B | PPC_ALTIVEC | \
@ -6394,7 +6394,7 @@ static void init_proc_970 (CPUPPCState *env)
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
PPC_FLOAT_STFIWX | \ PPC_FLOAT_STFIWX | \
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_64B | PPC_ALTIVEC | \ PPC_64B | PPC_ALTIVEC | \
@ -6496,7 +6496,7 @@ static void init_proc_970FX (CPUPPCState *env)
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
PPC_FLOAT_STFIWX | \ PPC_FLOAT_STFIWX | \
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_64B | PPC_ALTIVEC | \ PPC_64B | PPC_ALTIVEC | \
@ -6586,7 +6586,7 @@ static void init_proc_970GX (CPUPPCState *env)
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
PPC_FLOAT_STFIWX | \ PPC_FLOAT_STFIWX | \
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_64B | PPC_ALTIVEC | \ PPC_64B | PPC_ALTIVEC | \
@ -6677,7 +6677,7 @@ static void init_proc_970MP (CPUPPCState *env)
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
PPC_FLOAT_STFIWX | \ PPC_FLOAT_STFIWX | \
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
PPC_MEM_SYNC | PPC_MEM_EIEIO | \ PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_64B | PPC_ALTIVEC | \ PPC_64B | PPC_ALTIVEC | \