c40d479207
There is no need for a stub, since tb_invalidate_phys_addr can be excised altogether when TCG is disabled. This is a bit cleaner since it avoids using code that is clearly specific to user-mode emulation (it calls mmap_lock/unlock) for the !CONFIG_TCG case. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
513 lines
18 KiB
C
513 lines
18 KiB
C
/*
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* internal execution defines for qemu
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef EXEC_ALL_H
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#define EXEC_ALL_H
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#include "qemu-common.h"
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#include "exec/tb-context.h"
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#include "sysemu/cpus.h"
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/* allow to see translation results - the slowdown should be negligible, so we leave it */
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#define DEBUG_DISAS
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/* Page tracking code uses ram addresses in system mode, and virtual
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addresses in userspace mode. Define tb_page_addr_t to be an appropriate
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type. */
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#if defined(CONFIG_USER_ONLY)
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typedef abi_ulong tb_page_addr_t;
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#define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx
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#else
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typedef ram_addr_t tb_page_addr_t;
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#define TB_PAGE_ADDR_FMT RAM_ADDR_FMT
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#endif
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#include "qemu/log.h"
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void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb);
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void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
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target_ulong *data);
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void cpu_gen_init(void);
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/**
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* cpu_restore_state:
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* @cpu: the vCPU state is to be restore to
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* @searched_pc: the host PC the fault occurred at
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* @will_exit: true if the TB executed will be interrupted after some
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cpu adjustments. Required for maintaining the correct
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icount valus
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* @return: true if state was restored, false otherwise
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*
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* Attempt to restore the state for a fault occurring in translated
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* code. If the searched_pc is not in translated code no state is
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* restored and the function returns false.
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*/
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bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc, bool will_exit);
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void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu);
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void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
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TranslationBlock *tb_gen_code(CPUState *cpu,
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target_ulong pc, target_ulong cs_base,
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uint32_t flags,
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int cflags);
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void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
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void QEMU_NORETURN cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
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void QEMU_NORETURN cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
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#if !defined(CONFIG_USER_ONLY)
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void cpu_reloading_memory_map(void);
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/**
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* cpu_address_space_init:
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* @cpu: CPU to add this address space to
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* @asidx: integer index of this address space
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* @prefix: prefix to be used as name of address space
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* @mr: the root memory region of address space
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*
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* Add the specified address space to the CPU's cpu_ases list.
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* The address space added with @asidx 0 is the one used for the
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* convenience pointer cpu->as.
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* The target-specific code which registers ASes is responsible
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* for defining what semantics address space 0, 1, 2, etc have.
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*
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* Before the first call to this function, the caller must set
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* cpu->num_ases to the total number of address spaces it needs
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* to support.
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*
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* Note that with KVM only one address space is supported.
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*/
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void cpu_address_space_init(CPUState *cpu, int asidx,
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const char *prefix, MemoryRegion *mr);
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#endif
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#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
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/* cputlb.c */
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/**
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* tlb_flush_page:
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* @cpu: CPU whose TLB should be flushed
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* @addr: virtual address of page to be flushed
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*
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* Flush one page from the TLB of the specified CPU, for all
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* MMU indexes.
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*/
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void tlb_flush_page(CPUState *cpu, target_ulong addr);
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/**
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* tlb_flush_page_all_cpus:
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* @cpu: src CPU of the flush
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* @addr: virtual address of page to be flushed
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*
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* Flush one page from the TLB of the specified CPU, for all
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* MMU indexes.
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*/
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void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr);
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/**
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* tlb_flush_page_all_cpus_synced:
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* @cpu: src CPU of the flush
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* @addr: virtual address of page to be flushed
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*
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* Flush one page from the TLB of the specified CPU, for all MMU
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* indexes like tlb_flush_page_all_cpus except the source vCPUs work
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* is scheduled as safe work meaning all flushes will be complete once
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* the source vCPUs safe work is complete. This will depend on when
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* the guests translation ends the TB.
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*/
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void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr);
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/**
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* tlb_flush:
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* @cpu: CPU whose TLB should be flushed
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*
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* Flush the entire TLB for the specified CPU. Most CPU architectures
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* allow the implementation to drop entries from the TLB at any time
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* so this is generally safe. If more selective flushing is required
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* use one of the other functions for efficiency.
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*/
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void tlb_flush(CPUState *cpu);
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/**
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* tlb_flush_all_cpus:
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* @cpu: src CPU of the flush
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*/
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void tlb_flush_all_cpus(CPUState *src_cpu);
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/**
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* tlb_flush_all_cpus_synced:
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* @cpu: src CPU of the flush
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*
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* Like tlb_flush_all_cpus except this except the source vCPUs work is
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* scheduled as safe work meaning all flushes will be complete once
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* the source vCPUs safe work is complete. This will depend on when
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* the guests translation ends the TB.
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*/
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void tlb_flush_all_cpus_synced(CPUState *src_cpu);
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/**
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* tlb_flush_page_by_mmuidx:
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* @cpu: CPU whose TLB should be flushed
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* @addr: virtual address of page to be flushed
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush one page from the TLB of the specified CPU, for the specified
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* MMU indexes.
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*/
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void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr,
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uint16_t idxmap);
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/**
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* tlb_flush_page_by_mmuidx_all_cpus:
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* @cpu: Originating CPU of the flush
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* @addr: virtual address of page to be flushed
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush one page from the TLB of all CPUs, for the specified
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* MMU indexes.
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*/
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void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr,
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uint16_t idxmap);
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/**
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* tlb_flush_page_by_mmuidx_all_cpus_synced:
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* @cpu: Originating CPU of the flush
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* @addr: virtual address of page to be flushed
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush one page from the TLB of all CPUs, for the specified MMU
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* indexes like tlb_flush_page_by_mmuidx_all_cpus except the source
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* vCPUs work is scheduled as safe work meaning all flushes will be
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* complete once the source vCPUs safe work is complete. This will
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* depend on when the guests translation ends the TB.
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*/
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void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr,
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uint16_t idxmap);
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/**
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* tlb_flush_by_mmuidx:
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* @cpu: CPU whose TLB should be flushed
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* @wait: If true ensure synchronisation by exiting the cpu_loop
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush all entries from the TLB of the specified CPU, for the specified
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* MMU indexes.
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*/
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void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap);
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/**
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* tlb_flush_by_mmuidx_all_cpus:
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* @cpu: Originating CPU of the flush
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush all entries from all TLBs of all CPUs, for the specified
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* MMU indexes.
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*/
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void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap);
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/**
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* tlb_flush_by_mmuidx_all_cpus_synced:
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* @cpu: Originating CPU of the flush
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* @idxmap: bitmap of MMU indexes to flush
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*
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* Flush all entries from all TLBs of all CPUs, for the specified
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* MMU indexes like tlb_flush_by_mmuidx_all_cpus except except the source
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* vCPUs work is scheduled as safe work meaning all flushes will be
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* complete once the source vCPUs safe work is complete. This will
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* depend on when the guests translation ends the TB.
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*/
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void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
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/**
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* tlb_set_page_with_attrs:
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* @cpu: CPU to add this TLB entry for
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* @vaddr: virtual address of page to add entry for
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* @paddr: physical address of the page
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* @attrs: memory transaction attributes
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* @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
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* @mmu_idx: MMU index to insert TLB entry for
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* @size: size of the page in bytes
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*
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* Add an entry to this CPU's TLB (a mapping from virtual address
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* @vaddr to physical address @paddr) with the specified memory
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* transaction attributes. This is generally called by the target CPU
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* specific code after it has been called through the tlb_fill()
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* entry point and performed a successful page table walk to find
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* the physical address and attributes for the virtual address
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* which provoked the TLB miss.
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*
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* At most one entry for a given virtual address is permitted. Only a
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* single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
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* used by tlb_flush_page.
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*/
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void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
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hwaddr paddr, MemTxAttrs attrs,
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int prot, int mmu_idx, target_ulong size);
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/* tlb_set_page:
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*
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* This function is equivalent to calling tlb_set_page_with_attrs()
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* with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
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* as a convenience for CPUs which don't use memory transaction attributes.
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*/
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void tlb_set_page(CPUState *cpu, target_ulong vaddr,
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hwaddr paddr, int prot,
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int mmu_idx, target_ulong size);
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void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
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uintptr_t retaddr);
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#else
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static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
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{
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}
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static inline void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr)
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{
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}
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static inline void tlb_flush_page_all_cpus_synced(CPUState *src,
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target_ulong addr)
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{
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}
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static inline void tlb_flush(CPUState *cpu)
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{
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}
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static inline void tlb_flush_all_cpus(CPUState *src_cpu)
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{
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}
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static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu)
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{
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}
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static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
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target_ulong addr, uint16_t idxmap)
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{
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}
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static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
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{
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}
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static inline void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu,
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target_ulong addr,
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uint16_t idxmap)
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{
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}
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static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu,
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target_ulong addr,
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uint16_t idxmap)
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{
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}
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static inline void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap)
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{
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}
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static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
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uint16_t idxmap)
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{
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}
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#endif
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#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
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/* Estimated block size for TB allocation. */
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/* ??? The following is based on a 2015 survey of x86_64 host output.
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Better would seem to be some sort of dynamically sized TB array,
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adapting to the block sizes actually being produced. */
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#if defined(CONFIG_SOFTMMU)
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#define CODE_GEN_AVG_BLOCK_SIZE 400
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#else
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#define CODE_GEN_AVG_BLOCK_SIZE 150
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#endif
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/*
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* Translation Cache-related fields of a TB.
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* This struct exists just for convenience; we keep track of TB's in a binary
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* search tree, and the only fields needed to compare TB's in the tree are
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* @ptr and @size.
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* Note: the address of search data can be obtained by adding @size to @ptr.
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*/
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struct tb_tc {
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void *ptr; /* pointer to the translated code */
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size_t size;
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};
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struct TranslationBlock {
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target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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target_ulong cs_base; /* CS base for this block */
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uint32_t flags; /* flags defining in which context the code was generated */
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uint16_t size; /* size of target code for this block (1 <=
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size <= TARGET_PAGE_SIZE) */
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uint16_t icount;
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uint32_t cflags; /* compile flags */
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#define CF_COUNT_MASK 0x00007fff
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#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */
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#define CF_NOCACHE 0x00010000 /* To be freed after execution */
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#define CF_USE_ICOUNT 0x00020000
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#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held */
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#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */
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/* cflags' mask for hashing/comparison */
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#define CF_HASH_MASK \
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(CF_COUNT_MASK | CF_LAST_IO | CF_USE_ICOUNT | CF_PARALLEL)
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/* Per-vCPU dynamic tracing state used to generate this TB */
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uint32_t trace_vcpu_dstate;
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struct tb_tc tc;
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/* original tb when cflags has CF_NOCACHE */
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struct TranslationBlock *orig_tb;
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/* first and second physical page containing code. The lower bit
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of the pointer tells the index in page_next[].
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The list is protected by the TB's page('s) lock(s) */
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uintptr_t page_next[2];
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tb_page_addr_t page_addr[2];
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/* jmp_lock placed here to fill a 4-byte hole. Its documentation is below */
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QemuSpin jmp_lock;
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/* The following data are used to directly call another TB from
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* the code of this one. This can be done either by emitting direct or
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* indirect native jump instructions. These jumps are reset so that the TB
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* just continues its execution. The TB can be linked to another one by
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* setting one of the jump targets (or patching the jump instruction). Only
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* two of such jumps are supported.
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*/
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uint16_t jmp_reset_offset[2]; /* offset of original jump target */
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#define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated */
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uintptr_t jmp_target_arg[2]; /* target address or offset */
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/*
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* Each TB has a NULL-terminated list (jmp_list_head) of incoming jumps.
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* Each TB can have two outgoing jumps, and therefore can participate
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* in two lists. The list entries are kept in jmp_list_next[2]. The least
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* significant bit (LSB) of the pointers in these lists is used to encode
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* which of the two list entries is to be used in the pointed TB.
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*
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* List traversals are protected by jmp_lock. The destination TB of each
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* outgoing jump is kept in jmp_dest[] so that the appropriate jmp_lock
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* can be acquired from any origin TB.
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*
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* jmp_dest[] are tagged pointers as well. The LSB is set when the TB is
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* being invalidated, so that no further outgoing jumps from it can be set.
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*
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* jmp_lock also protects the CF_INVALID cflag; a jump must not be chained
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* to a destination TB that has CF_INVALID set.
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*/
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uintptr_t jmp_list_head;
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uintptr_t jmp_list_next[2];
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uintptr_t jmp_dest[2];
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};
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extern bool parallel_cpus;
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/* Hide the atomic_read to make code a little easier on the eyes */
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static inline uint32_t tb_cflags(const TranslationBlock *tb)
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{
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return atomic_read(&tb->cflags);
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}
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/* current cflags for hashing/comparison */
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static inline uint32_t curr_cflags(void)
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{
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return (parallel_cpus ? CF_PARALLEL : 0)
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| (use_icount ? CF_USE_ICOUNT : 0);
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}
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/* TranslationBlock invalidate API */
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#if defined(CONFIG_USER_ONLY)
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void tb_invalidate_phys_addr(target_ulong addr);
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void tb_invalidate_phys_range(target_ulong start, target_ulong end);
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#else
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void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
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#endif
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void tb_flush(CPUState *cpu);
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void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
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TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
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target_ulong cs_base, uint32_t flags,
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uint32_t cf_mask);
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void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
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/* GETPC is the true target of the return instruction that we'll execute. */
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#if defined(CONFIG_TCG_INTERPRETER)
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extern uintptr_t tci_tb_ptr;
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# define GETPC() tci_tb_ptr
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#else
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# define GETPC() \
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((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
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#endif
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/* The true return address will often point to a host insn that is part of
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the next translated guest insn. Adjust the address backward to point to
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the middle of the call insn. Subtracting one would do the job except for
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several compressed mode architectures (arm, mips) which set the low bit
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to indicate the compressed mode; subtracting two works around that. It
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is also the case that there are no host isas that contain a call insn
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smaller than 4 bytes, so we don't worry about special-casing this. */
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#define GETPC_ADJ 2
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#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_DEBUG_TCG)
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void assert_no_pages_locked(void);
|
|
#else
|
|
static inline void assert_no_pages_locked(void)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
/**
|
|
* iotlb_to_section:
|
|
* @cpu: CPU performing the access
|
|
* @index: TCG CPU IOTLB entry
|
|
*
|
|
* Given a TCG CPU IOTLB entry, return the MemoryRegionSection that
|
|
* it refers to. @index will have been initially created and returned
|
|
* by memory_region_section_get_iotlb().
|
|
*/
|
|
struct MemoryRegionSection *iotlb_to_section(CPUState *cpu,
|
|
hwaddr index, MemTxAttrs attrs);
|
|
|
|
void tlb_fill(CPUState *cpu, target_ulong addr, int size,
|
|
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
|
|
|
|
#endif
|
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
void mmap_lock(void);
|
|
void mmap_unlock(void);
|
|
bool have_mmap_lock(void);
|
|
|
|
static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
|
|
{
|
|
return addr;
|
|
}
|
|
#else
|
|
static inline void mmap_lock(void) {}
|
|
static inline void mmap_unlock(void) {}
|
|
|
|
/* cputlb.c */
|
|
tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr);
|
|
|
|
void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
|
|
void tlb_set_dirty(CPUState *cpu, target_ulong vaddr);
|
|
|
|
/* exec.c */
|
|
void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr);
|
|
|
|
MemoryRegionSection *
|
|
address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
|
|
hwaddr *xlat, hwaddr *plen,
|
|
MemTxAttrs attrs, int *prot);
|
|
hwaddr memory_region_section_get_iotlb(CPUState *cpu,
|
|
MemoryRegionSection *section,
|
|
target_ulong vaddr,
|
|
hwaddr paddr, hwaddr xlat,
|
|
int prot,
|
|
target_ulong *address);
|
|
bool memory_region_is_unassigned(MemoryRegion *mr);
|
|
|
|
#endif
|
|
|
|
/* vl.c */
|
|
extern int singlestep;
|
|
|
|
#endif
|