7fe48483cd
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1110 c046a42c-6fe2-441c-8c8c-71466251a162
726 lines
17 KiB
C
726 lines
17 KiB
C
/*
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* defines common to all virtual CPUs
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef CPU_ALL_H
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#define CPU_ALL_H
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#if defined(__arm__) || defined(__sparc__)
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#define WORDS_ALIGNED
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#endif
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/* some important defines:
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*
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* WORDS_ALIGNED : if defined, the host cpu can only make word aligned
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* memory accesses.
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*
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* WORDS_BIGENDIAN : if defined, the host cpu is big endian and
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* otherwise little endian.
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*
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* (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
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*
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* TARGET_WORDS_BIGENDIAN : same for target cpu
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*/
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#include "bswap.h"
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#if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
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#define BSWAP_NEEDED
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#endif
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#ifdef BSWAP_NEEDED
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static inline uint16_t tswap16(uint16_t s)
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{
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return bswap16(s);
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}
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static inline uint32_t tswap32(uint32_t s)
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{
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return bswap32(s);
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}
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static inline uint64_t tswap64(uint64_t s)
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{
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return bswap64(s);
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}
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static inline void tswap16s(uint16_t *s)
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{
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*s = bswap16(*s);
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}
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static inline void tswap32s(uint32_t *s)
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{
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*s = bswap32(*s);
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}
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static inline void tswap64s(uint64_t *s)
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{
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*s = bswap64(*s);
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}
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#else
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static inline uint16_t tswap16(uint16_t s)
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{
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return s;
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}
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static inline uint32_t tswap32(uint32_t s)
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{
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return s;
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}
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static inline uint64_t tswap64(uint64_t s)
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{
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return s;
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}
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static inline void tswap16s(uint16_t *s)
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{
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}
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static inline void tswap32s(uint32_t *s)
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{
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}
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static inline void tswap64s(uint64_t *s)
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{
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}
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#endif
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#if TARGET_LONG_SIZE == 4
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#define tswapl(s) tswap32(s)
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#define tswapls(s) tswap32s((uint32_t *)(s))
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#else
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#define tswapl(s) tswap64(s)
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#define tswapls(s) tswap64s((uint64_t *)(s))
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#endif
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/* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
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typedef union {
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double d;
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#if !defined(WORDS_BIGENDIAN) && !defined(__arm__)
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struct {
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uint32_t lower;
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uint32_t upper;
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} l;
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#else
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struct {
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uint32_t upper;
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uint32_t lower;
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} l;
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#endif
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uint64_t ll;
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} CPU_DoubleU;
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/* CPU memory access without any memory or io remapping */
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/*
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* the generic syntax for the memory accesses is:
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*
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* load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
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*
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* store: st{type}{size}{endian}_{access_type}(ptr, val)
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*
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* type is:
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* (empty): integer access
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* f : float access
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*
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* sign is:
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* (empty): for floats or 32 bit size
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* u : unsigned
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* s : signed
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*
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* size is:
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* b: 8 bits
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* w: 16 bits
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* l: 32 bits
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* q: 64 bits
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*
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* endian is:
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* (empty): target cpu endianness or 8 bit access
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* r : reversed target cpu endianness (not implemented yet)
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* be : big endian (not implemented yet)
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* le : little endian (not implemented yet)
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*
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* access_type is:
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* raw : host memory access
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* user : user mode access using soft MMU
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* kernel : kernel mode access using soft MMU
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*/
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static inline int ldub_raw(void *ptr)
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{
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return *(uint8_t *)ptr;
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}
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static inline int ldsb_raw(void *ptr)
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{
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return *(int8_t *)ptr;
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}
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static inline void stb_raw(void *ptr, int v)
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{
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*(uint8_t *)ptr = v;
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}
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/* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
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kernel handles unaligned load/stores may give better results, but
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it is a system wide setting : bad */
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#if !defined(TARGET_WORDS_BIGENDIAN) && (defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED))
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/* conservative code for little endian unaligned accesses */
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static inline int lduw_raw(void *ptr)
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{
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#ifdef __powerpc__
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int val;
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__asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
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return val;
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#else
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uint8_t *p = ptr;
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return p[0] | (p[1] << 8);
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#endif
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}
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static inline int ldsw_raw(void *ptr)
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{
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#ifdef __powerpc__
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int val;
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__asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
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return (int16_t)val;
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#else
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uint8_t *p = ptr;
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return (int16_t)(p[0] | (p[1] << 8));
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#endif
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}
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static inline int ldl_raw(void *ptr)
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{
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#ifdef __powerpc__
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int val;
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__asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
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return val;
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#else
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uint8_t *p = ptr;
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return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
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#endif
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}
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static inline uint64_t ldq_raw(void *ptr)
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{
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uint8_t *p = ptr;
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uint32_t v1, v2;
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v1 = ldl_raw(p);
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v2 = ldl_raw(p + 4);
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return v1 | ((uint64_t)v2 << 32);
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}
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static inline void stw_raw(void *ptr, int v)
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{
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#ifdef __powerpc__
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__asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
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#else
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uint8_t *p = ptr;
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p[0] = v;
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p[1] = v >> 8;
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#endif
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}
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static inline void stl_raw(void *ptr, int v)
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{
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#ifdef __powerpc__
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__asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
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#else
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uint8_t *p = ptr;
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p[0] = v;
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p[1] = v >> 8;
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p[2] = v >> 16;
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p[3] = v >> 24;
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#endif
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}
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static inline void stq_raw(void *ptr, uint64_t v)
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{
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uint8_t *p = ptr;
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stl_raw(p, (uint32_t)v);
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stl_raw(p + 4, v >> 32);
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}
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/* float access */
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static inline float ldfl_raw(void *ptr)
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{
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union {
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float f;
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uint32_t i;
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} u;
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u.i = ldl_raw(ptr);
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return u.f;
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}
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static inline void stfl_raw(void *ptr, float v)
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{
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union {
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float f;
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uint32_t i;
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} u;
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u.f = v;
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stl_raw(ptr, u.i);
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}
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static inline double ldfq_raw(void *ptr)
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{
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CPU_DoubleU u;
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u.l.lower = ldl_raw(ptr);
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u.l.upper = ldl_raw(ptr + 4);
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return u.d;
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}
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static inline void stfq_raw(void *ptr, double v)
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{
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CPU_DoubleU u;
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u.d = v;
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stl_raw(ptr, u.l.lower);
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stl_raw(ptr + 4, u.l.upper);
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}
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#elif defined(TARGET_WORDS_BIGENDIAN) && (!defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED))
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static inline int lduw_raw(void *ptr)
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{
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#if defined(__i386__)
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int val;
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asm volatile ("movzwl %1, %0\n"
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"xchgb %b0, %h0\n"
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: "=q" (val)
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: "m" (*(uint16_t *)ptr));
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return val;
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#else
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uint8_t *b = (uint8_t *) ptr;
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return ((b[0] << 8) | b[1]);
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#endif
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}
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static inline int ldsw_raw(void *ptr)
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{
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#if defined(__i386__)
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int val;
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asm volatile ("movzwl %1, %0\n"
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"xchgb %b0, %h0\n"
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: "=q" (val)
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: "m" (*(uint16_t *)ptr));
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return (int16_t)val;
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#else
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uint8_t *b = (uint8_t *) ptr;
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return (int16_t)((b[0] << 8) | b[1]);
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#endif
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}
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static inline int ldl_raw(void *ptr)
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{
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#if defined(__i386__) || defined(__x86_64__)
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int val;
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asm volatile ("movl %1, %0\n"
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"bswap %0\n"
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: "=r" (val)
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: "m" (*(uint32_t *)ptr));
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return val;
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#else
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uint8_t *b = (uint8_t *) ptr;
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return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
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#endif
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}
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static inline uint64_t ldq_raw(void *ptr)
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{
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uint32_t a,b;
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a = ldl_raw(ptr);
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b = ldl_raw(ptr+4);
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return (((uint64_t)a<<32)|b);
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}
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static inline void stw_raw(void *ptr, int v)
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{
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#if defined(__i386__)
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asm volatile ("xchgb %b0, %h0\n"
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"movw %w0, %1\n"
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: "=q" (v)
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: "m" (*(uint16_t *)ptr), "0" (v));
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#else
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uint8_t *d = (uint8_t *) ptr;
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d[0] = v >> 8;
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d[1] = v;
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#endif
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}
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static inline void stl_raw(void *ptr, int v)
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{
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#if defined(__i386__) || defined(__x86_64__)
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asm volatile ("bswap %0\n"
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"movl %0, %1\n"
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: "=r" (v)
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: "m" (*(uint32_t *)ptr), "0" (v));
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#else
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uint8_t *d = (uint8_t *) ptr;
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d[0] = v >> 24;
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d[1] = v >> 16;
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d[2] = v >> 8;
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d[3] = v;
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#endif
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}
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static inline void stq_raw(void *ptr, uint64_t v)
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{
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stl_raw(ptr, v >> 32);
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stl_raw(ptr + 4, v);
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}
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/* float access */
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static inline float ldfl_raw(void *ptr)
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{
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union {
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float f;
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uint32_t i;
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} u;
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u.i = ldl_raw(ptr);
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return u.f;
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}
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static inline void stfl_raw(void *ptr, float v)
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{
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union {
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float f;
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uint32_t i;
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} u;
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u.f = v;
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stl_raw(ptr, u.i);
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}
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static inline double ldfq_raw(void *ptr)
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{
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CPU_DoubleU u;
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u.l.upper = ldl_raw(ptr);
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u.l.lower = ldl_raw(ptr + 4);
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return u.d;
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}
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static inline void stfq_raw(void *ptr, double v)
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{
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CPU_DoubleU u;
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u.d = v;
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stl_raw(ptr, u.l.upper);
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stl_raw(ptr + 4, u.l.lower);
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}
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#else
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static inline int lduw_raw(void *ptr)
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{
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return *(uint16_t *)ptr;
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}
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static inline int ldsw_raw(void *ptr)
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{
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return *(int16_t *)ptr;
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}
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static inline int ldl_raw(void *ptr)
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{
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return *(uint32_t *)ptr;
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}
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static inline uint64_t ldq_raw(void *ptr)
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{
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return *(uint64_t *)ptr;
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}
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static inline void stw_raw(void *ptr, int v)
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{
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*(uint16_t *)ptr = v;
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}
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static inline void stl_raw(void *ptr, int v)
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{
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*(uint32_t *)ptr = v;
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}
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static inline void stq_raw(void *ptr, uint64_t v)
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{
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*(uint64_t *)ptr = v;
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}
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/* float access */
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static inline float ldfl_raw(void *ptr)
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{
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return *(float *)ptr;
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}
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static inline double ldfq_raw(void *ptr)
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{
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return *(double *)ptr;
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}
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static inline void stfl_raw(void *ptr, float v)
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{
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*(float *)ptr = v;
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}
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static inline void stfq_raw(void *ptr, double v)
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{
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*(double *)ptr = v;
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}
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#endif
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/* MMU memory access macros */
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#if defined(CONFIG_USER_ONLY)
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/* if user mode, no other memory access functions */
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#define ldub(p) ldub_raw(p)
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#define ldsb(p) ldsb_raw(p)
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#define lduw(p) lduw_raw(p)
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#define ldsw(p) ldsw_raw(p)
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#define ldl(p) ldl_raw(p)
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#define ldq(p) ldq_raw(p)
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#define ldfl(p) ldfl_raw(p)
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#define ldfq(p) ldfq_raw(p)
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#define stb(p, v) stb_raw(p, v)
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#define stw(p, v) stw_raw(p, v)
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#define stl(p, v) stl_raw(p, v)
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#define stq(p, v) stq_raw(p, v)
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#define stfl(p, v) stfl_raw(p, v)
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#define stfq(p, v) stfq_raw(p, v)
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#define ldub_code(p) ldub_raw(p)
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#define ldsb_code(p) ldsb_raw(p)
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#define lduw_code(p) lduw_raw(p)
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#define ldsw_code(p) ldsw_raw(p)
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#define ldl_code(p) ldl_raw(p)
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#define ldub_kernel(p) ldub_raw(p)
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#define ldsb_kernel(p) ldsb_raw(p)
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#define lduw_kernel(p) lduw_raw(p)
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#define ldsw_kernel(p) ldsw_raw(p)
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#define ldl_kernel(p) ldl_raw(p)
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#define ldfl_kernel(p) ldfl_raw(p)
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#define ldfq_kernel(p) ldfq_raw(p)
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#define stb_kernel(p, v) stb_raw(p, v)
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#define stw_kernel(p, v) stw_raw(p, v)
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#define stl_kernel(p, v) stl_raw(p, v)
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#define stq_kernel(p, v) stq_raw(p, v)
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#define stfl_kernel(p, v) stfl_raw(p, v)
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#define stfq_kernel(p, vt) stfq_raw(p, v)
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#endif /* defined(CONFIG_USER_ONLY) */
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/* page related stuff */
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#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
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#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
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#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
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extern unsigned long qemu_real_host_page_size;
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extern unsigned long qemu_host_page_bits;
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extern unsigned long qemu_host_page_size;
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extern unsigned long qemu_host_page_mask;
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#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
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/* same as PROT_xxx */
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#define PAGE_READ 0x0001
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#define PAGE_WRITE 0x0002
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#define PAGE_EXEC 0x0004
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#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
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#define PAGE_VALID 0x0008
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/* original state of the write flag (used when tracking self-modifying
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code */
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#define PAGE_WRITE_ORG 0x0010
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void page_dump(FILE *f);
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int page_get_flags(unsigned long address);
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void page_set_flags(unsigned long start, unsigned long end, int flags);
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void page_unprotect_range(uint8_t *data, unsigned long data_size);
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#define SINGLE_CPU_DEFINES
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#ifdef SINGLE_CPU_DEFINES
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#if defined(TARGET_I386)
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#define CPUState CPUX86State
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#define cpu_init cpu_x86_init
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#define cpu_exec cpu_x86_exec
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#define cpu_gen_code cpu_x86_gen_code
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#define cpu_signal_handler cpu_x86_signal_handler
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#elif defined(TARGET_ARM)
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#define CPUState CPUARMState
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#define cpu_init cpu_arm_init
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#define cpu_exec cpu_arm_exec
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#define cpu_gen_code cpu_arm_gen_code
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#define cpu_signal_handler cpu_arm_signal_handler
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#elif defined(TARGET_SPARC)
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#define CPUState CPUSPARCState
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#define cpu_init cpu_sparc_init
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#define cpu_exec cpu_sparc_exec
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#define cpu_gen_code cpu_sparc_gen_code
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#define cpu_signal_handler cpu_sparc_signal_handler
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#elif defined(TARGET_PPC)
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#define CPUState CPUPPCState
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#define cpu_init cpu_ppc_init
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#define cpu_exec cpu_ppc_exec
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#define cpu_gen_code cpu_ppc_gen_code
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#define cpu_signal_handler cpu_ppc_signal_handler
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#else
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#error unsupported target CPU
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#endif
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#endif /* SINGLE_CPU_DEFINES */
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void cpu_dump_state(CPUState *env, FILE *f,
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int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
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int flags);
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void cpu_abort(CPUState *env, const char *fmt, ...);
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extern CPUState *cpu_single_env;
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extern int code_copy_enabled;
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#define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */
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#define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */
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#define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
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#define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */
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void cpu_interrupt(CPUState *s, int mask);
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void cpu_reset_interrupt(CPUState *env, int mask);
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int cpu_breakpoint_insert(CPUState *env, target_ulong pc);
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int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
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void cpu_single_step(CPUState *env, int enabled);
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void cpu_reset(CPUState *s);
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/* Return the physical page corresponding to a virtual one. Use it
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only for debugging because no protection checks are done. Return -1
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if no page found. */
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target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
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#define CPU_LOG_TB_OUT_ASM (1 << 0)
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#define CPU_LOG_TB_IN_ASM (1 << 1)
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#define CPU_LOG_TB_OP (1 << 2)
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#define CPU_LOG_TB_OP_OPT (1 << 3)
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#define CPU_LOG_INT (1 << 4)
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#define CPU_LOG_EXEC (1 << 5)
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#define CPU_LOG_PCALL (1 << 6)
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#define CPU_LOG_IOPORT (1 << 7)
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#define CPU_LOG_TB_CPU (1 << 8)
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/* define log items */
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typedef struct CPULogItem {
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int mask;
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const char *name;
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const char *help;
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} CPULogItem;
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extern CPULogItem cpu_log_items[];
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void cpu_set_log(int log_flags);
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|
void cpu_set_log_filename(const char *filename);
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int cpu_str_to_log_mask(const char *str);
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/* IO ports API */
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/* NOTE: as these functions may be even used when there is an isa
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brige on non x86 targets, we always defined them */
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#ifndef NO_CPU_IO_DEFS
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void cpu_outb(CPUState *env, int addr, int val);
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void cpu_outw(CPUState *env, int addr, int val);
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void cpu_outl(CPUState *env, int addr, int val);
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int cpu_inb(CPUState *env, int addr);
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int cpu_inw(CPUState *env, int addr);
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int cpu_inl(CPUState *env, int addr);
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#endif
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|
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/* memory API */
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|
|
|
extern int phys_ram_size;
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|
extern int phys_ram_fd;
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|
extern uint8_t *phys_ram_base;
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|
extern uint8_t *phys_ram_dirty;
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|
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/* physical memory access */
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|
#define IO_MEM_NB_ENTRIES 256
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#define TLB_INVALID_MASK (1 << 3)
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#define IO_MEM_SHIFT 4
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#define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
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|
#define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
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|
#define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
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#define IO_MEM_CODE (3 << IO_MEM_SHIFT) /* used internally, never use directly */
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#define IO_MEM_NOTDIRTY (4 << IO_MEM_SHIFT) /* used internally, never use directly */
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|
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typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
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typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
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|
|
void cpu_register_physical_memory(target_phys_addr_t start_addr,
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|
unsigned long size,
|
|
unsigned long phys_offset);
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|
int cpu_register_io_memory(int io_index,
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|
CPUReadMemoryFunc **mem_read,
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|
CPUWriteMemoryFunc **mem_write,
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|
void *opaque);
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|
|
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void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
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|
int len, int is_write);
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|
static inline void cpu_physical_memory_read(target_phys_addr_t addr,
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|
uint8_t *buf, int len)
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|
{
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|
cpu_physical_memory_rw(addr, buf, len, 0);
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|
}
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|
static inline void cpu_physical_memory_write(target_phys_addr_t addr,
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|
const uint8_t *buf, int len)
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|
{
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|
cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
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|
}
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|
|
|
int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
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|
uint8_t *buf, int len, int is_write);
|
|
|
|
/* read dirty bit (return 0 or 1) */
|
|
static inline int cpu_physical_memory_is_dirty(target_ulong addr)
|
|
{
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|
return phys_ram_dirty[addr >> TARGET_PAGE_BITS];
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|
}
|
|
|
|
static inline void cpu_physical_memory_set_dirty(target_ulong addr)
|
|
{
|
|
phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 1;
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|
}
|
|
|
|
void cpu_physical_memory_reset_dirty(target_ulong start, target_ulong end);
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|
|
|
#endif /* CPU_ALL_H */
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