d537cf6c86
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2635 c046a42c-6fe2-441c-8c8c-71466251a162
444 lines
12 KiB
C
444 lines
12 KiB
C
/*
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* Arm PrimeCell PL181 MultiMedia Card Interface
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*
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* Copyright (c) 2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL.
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*/
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#include "vl.h"
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#include "sd.h"
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//#define DEBUG_PL181 1
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#ifdef DEBUG_PL181
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#define DPRINTF(fmt, args...) \
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do { printf("pl181: " fmt , ##args); } while (0)
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#else
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#define DPRINTF(fmt, args...) do {} while(0)
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#endif
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#define PL181_FIFO_LEN 16
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typedef struct {
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SDState *card;
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uint32_t base;
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uint32_t clock;
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uint32_t power;
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uint32_t cmdarg;
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uint32_t cmd;
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uint32_t datatimer;
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uint32_t datalength;
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uint32_t respcmd;
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uint32_t response[4];
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uint32_t datactrl;
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uint32_t datacnt;
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uint32_t status;
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uint32_t mask[2];
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uint32_t fifocnt;
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int fifo_pos;
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int fifo_len;
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uint32_t fifo[PL181_FIFO_LEN];
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qemu_irq irq[2];
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} pl181_state;
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#define PL181_CMD_INDEX 0x3f
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#define PL181_CMD_RESPONSE (1 << 6)
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#define PL181_CMD_LONGRESP (1 << 7)
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#define PL181_CMD_INTERRUPT (1 << 8)
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#define PL181_CMD_PENDING (1 << 9)
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#define PL181_CMD_ENABLE (1 << 10)
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#define PL181_DATA_ENABLE (1 << 0)
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#define PL181_DATA_DIRECTION (1 << 1)
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#define PL181_DATA_MODE (1 << 2)
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#define PL181_DATA_DMAENABLE (1 << 3)
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#define PL181_STATUS_CMDCRCFAIL (1 << 0)
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#define PL181_STATUS_DATACRCFAIL (1 << 1)
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#define PL181_STATUS_CMDTIMEOUT (1 << 2)
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#define PL181_STATUS_DATATIMEOUT (1 << 3)
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#define PL181_STATUS_TXUNDERRUN (1 << 4)
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#define PL181_STATUS_RXOVERRUN (1 << 5)
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#define PL181_STATUS_CMDRESPEND (1 << 6)
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#define PL181_STATUS_CMDSENT (1 << 7)
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#define PL181_STATUS_DATAEND (1 << 8)
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#define PL181_STATUS_DATABLOCKEND (1 << 10)
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#define PL181_STATUS_CMDACTIVE (1 << 11)
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#define PL181_STATUS_TXACTIVE (1 << 12)
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#define PL181_STATUS_RXACTIVE (1 << 13)
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#define PL181_STATUS_TXFIFOHALFEMPTY (1 << 14)
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#define PL181_STATUS_RXFIFOHALFFULL (1 << 15)
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#define PL181_STATUS_TXFIFOFULL (1 << 16)
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#define PL181_STATUS_RXFIFOFULL (1 << 17)
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#define PL181_STATUS_TXFIFOEMPTY (1 << 18)
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#define PL181_STATUS_RXFIFOEMPTY (1 << 19)
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#define PL181_STATUS_TXDATAAVLBL (1 << 20)
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#define PL181_STATUS_RXDATAAVLBL (1 << 21)
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#define PL181_STATUS_TX_FIFO (PL181_STATUS_TXACTIVE \
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|PL181_STATUS_TXFIFOHALFEMPTY \
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|PL181_STATUS_TXFIFOFULL \
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|PL181_STATUS_TXFIFOEMPTY \
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|PL181_STATUS_TXDATAAVLBL)
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#define PL181_STATUS_RX_FIFO (PL181_STATUS_RXACTIVE \
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|PL181_STATUS_RXFIFOHALFFULL \
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|PL181_STATUS_RXFIFOFULL \
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|PL181_STATUS_RXFIFOEMPTY \
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|PL181_STATUS_RXDATAAVLBL)
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static const unsigned char pl181_id[] =
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{ 0x81, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
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static void pl181_update(pl181_state *s)
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{
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int i;
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for (i = 0; i < 2; i++) {
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qemu_set_irq(s->irq[i], (s->status & s->mask[i]) != 0);
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}
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}
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static void pl181_fifo_push(pl181_state *s, uint32_t value)
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{
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int n;
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if (s->fifo_len == PL181_FIFO_LEN) {
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fprintf(stderr, "pl181: FIFO overflow\n");
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return;
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}
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n = (s->fifo_pos + s->fifo_len) & (PL181_FIFO_LEN - 1);
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s->fifo_len++;
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s->fifo[n] = value;
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DPRINTF("FIFO push %08x\n", (int)value);
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}
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static uint32_t pl181_fifo_pop(pl181_state *s)
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{
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uint32_t value;
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if (s->fifo_len == 0) {
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fprintf(stderr, "pl181: FIFO underflow\n");
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return 0;
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}
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value = s->fifo[s->fifo_pos];
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s->fifo_len--;
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s->fifo_pos = (s->fifo_pos + 1) & (PL181_FIFO_LEN - 1);
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DPRINTF("FIFO pop %08x\n", (int)value);
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return value;
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}
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static void pl181_send_command(pl181_state *s)
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{
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struct sd_request_s request;
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uint8_t response[16];
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int rlen;
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request.cmd = s->cmd & PL181_CMD_INDEX;
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request.arg = s->cmdarg;
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DPRINTF("Command %d %08x\n", request.cmd, request.arg);
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rlen = sd_do_command(s->card, &request, response);
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if (rlen < 0)
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goto error;
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if (s->cmd & PL181_CMD_RESPONSE) {
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#define RWORD(n) ((response[n] << 24) | (response[n + 1] << 16) \
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| (response[n + 2] << 8) | response[n + 3])
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if (rlen == 0 || (rlen == 4 && (s->cmd & PL181_CMD_LONGRESP)))
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goto error;
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if (rlen != 4 && rlen != 16)
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goto error;
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s->response[0] = RWORD(0);
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if (rlen == 4) {
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s->response[1] = s->response[2] = s->response[3] = 0;
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} else {
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s->response[1] = RWORD(4);
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s->response[2] = RWORD(8);
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s->response[3] = RWORD(12) & ~1;
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}
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DPRINTF("Response recieved\n");
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s->status |= PL181_STATUS_CMDRESPEND;
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#undef RWORD
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} else {
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DPRINTF("Command sent\n");
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s->status |= PL181_STATUS_CMDSENT;
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}
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return;
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error:
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DPRINTF("Timeout\n");
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s->status |= PL181_STATUS_CMDTIMEOUT;
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}
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/* Transfer data between teh card and the FIFO. This is complicated by
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the FIFO holding 32-bit words and the card taking data in single byte
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chunks. FIFO bytes are transferred in little-endian order. */
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static void pl181_fifo_run(pl181_state *s)
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{
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uint32_t bits;
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uint32_t value;
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int n;
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int limit;
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int is_read;
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is_read = (s->datactrl & PL181_DATA_DIRECTION) != 0;
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if (s->datacnt != 0 && (!is_read || sd_data_ready(s->card))) {
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limit = is_read ? PL181_FIFO_LEN : 0;
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n = 0;
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value = 0;
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while (s->datacnt && s->fifo_len != limit) {
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if (is_read) {
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value |= (uint32_t)sd_read_data(s->card) << (n * 8);
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n++;
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if (n == 4) {
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pl181_fifo_push(s, value);
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value = 0;
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n = 0;
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}
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} else {
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if (n == 0) {
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value = pl181_fifo_pop(s);
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n = 4;
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}
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sd_write_data(s->card, value & 0xff);
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value >>= 8;
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n--;
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}
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s->datacnt--;
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}
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if (n && is_read) {
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pl181_fifo_push(s, value);
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}
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}
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s->status &= ~(PL181_STATUS_RX_FIFO | PL181_STATUS_TX_FIFO);
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if (s->datacnt == 0) {
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s->status |= PL181_STATUS_DATAEND;
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/* HACK: */
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s->status |= PL181_STATUS_DATABLOCKEND;
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DPRINTF("Transfer Complete\n");
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}
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if (s->datacnt == 0 && s->fifocnt == 0) {
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s->datactrl &= ~PL181_DATA_ENABLE;
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DPRINTF("Data engine idle\n");
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} else {
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/* Update FIFO bits. */
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bits = PL181_STATUS_TXACTIVE | PL181_STATUS_RXACTIVE;
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if (s->fifo_len == 0) {
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bits |= PL181_STATUS_TXFIFOEMPTY;
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bits |= PL181_STATUS_RXFIFOEMPTY;
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} else {
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bits |= PL181_STATUS_TXDATAAVLBL;
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bits |= PL181_STATUS_RXDATAAVLBL;
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}
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if (s->fifo_len == 16) {
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bits |= PL181_STATUS_TXFIFOFULL;
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bits |= PL181_STATUS_RXFIFOFULL;
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}
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if (s->fifo_len <= 8) {
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bits |= PL181_STATUS_TXFIFOHALFEMPTY;
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}
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if (s->fifo_len >= 8) {
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bits |= PL181_STATUS_RXFIFOHALFFULL;
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}
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if (s->datactrl & PL181_DATA_DIRECTION) {
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bits &= PL181_STATUS_RX_FIFO;
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} else {
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bits &= PL181_STATUS_TX_FIFO;
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}
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s->status |= bits;
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}
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}
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static uint32_t pl181_read(void *opaque, target_phys_addr_t offset)
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{
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pl181_state *s = (pl181_state *)opaque;
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offset -= s->base;
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if (offset >= 0xfe0 && offset < 0x1000) {
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return pl181_id[(offset - 0xfe0) >> 2];
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}
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switch (offset) {
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case 0x00: /* Power */
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return s->power;
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case 0x04: /* Clock */
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return s->clock;
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case 0x08: /* Argument */
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return s->cmdarg;
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case 0x0c: /* Command */
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return s->cmd;
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case 0x10: /* RespCmd */
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return s->respcmd;
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case 0x14: /* Response0 */
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return s->response[0];
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case 0x18: /* Response1 */
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return s->response[1];
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case 0x1c: /* Response2 */
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return s->response[2];
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case 0x20: /* Response3 */
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return s->response[3];
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case 0x24: /* DataTimer */
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return s->datatimer;
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case 0x28: /* DataLength */
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return s->datalength;
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case 0x2c: /* DataCtrl */
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return s->datactrl;
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case 0x30: /* DataCnt */
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return s->datacnt;
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case 0x34: /* Status */
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return s->status;
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case 0x3c: /* Mask0 */
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return s->mask[0];
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case 0x40: /* Mask1 */
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return s->mask[1];
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case 0x48: /* FifoCnt */
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return s->fifocnt;
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case 0x80: case 0x84: case 0x88: case 0x8c: /* FifoData */
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case 0x90: case 0x94: case 0x98: case 0x9c:
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case 0xa0: case 0xa4: case 0xa8: case 0xac:
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case 0xb0: case 0xb4: case 0xb8: case 0xbc:
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if (s->fifocnt == 0) {
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fprintf(stderr, "pl181: Unexpected FIFO read\n");
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return 0;
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} else {
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uint32_t value;
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s->fifocnt--;
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value = pl181_fifo_pop(s);
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pl181_fifo_run(s);
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pl181_update(s);
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return value;
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}
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default:
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cpu_abort (cpu_single_env, "pl181_read: Bad offset %x\n", offset);
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return 0;
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}
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}
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static void pl181_write(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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pl181_state *s = (pl181_state *)opaque;
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offset -= s->base;
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switch (offset) {
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case 0x00: /* Power */
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s->power = value & 0xff;
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break;
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case 0x04: /* Clock */
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s->clock = value & 0xff;
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break;
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case 0x08: /* Argument */
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s->cmdarg = value;
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break;
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case 0x0c: /* Command */
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s->cmd = value;
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if (s->cmd & PL181_CMD_ENABLE) {
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if (s->cmd & PL181_CMD_INTERRUPT) {
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fprintf(stderr, "pl181: Interrupt mode not implemented\n");
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abort();
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} if (s->cmd & PL181_CMD_PENDING) {
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fprintf(stderr, "pl181: Pending commands not implemented\n");
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abort();
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} else {
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pl181_send_command(s);
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pl181_fifo_run(s);
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}
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/* The command has completed one way or the other. */
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s->cmd &= ~PL181_CMD_ENABLE;
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}
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break;
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case 0x24: /* DataTimer */
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s->datatimer = value;
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break;
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case 0x28: /* DataLength */
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s->datalength = value & 0xffff;
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break;
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case 0x2c: /* DataCtrl */
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s->datactrl = value & 0xff;
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if (value & PL181_DATA_ENABLE) {
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s->datacnt = s->datalength;
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s->fifocnt = (s->datalength + 3) >> 2;
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pl181_fifo_run(s);
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}
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break;
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case 0x38: /* Clear */
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s->status &= ~(value & 0x7ff);
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break;
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case 0x3c: /* Mask0 */
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s->mask[0] = value;
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break;
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case 0x40: /* Mask1 */
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s->mask[1] = value;
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break;
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case 0x80: case 0x84: case 0x88: case 0x8c: /* FifoData */
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case 0x90: case 0x94: case 0x98: case 0x9c:
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case 0xa0: case 0xa4: case 0xa8: case 0xac:
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case 0xb0: case 0xb4: case 0xb8: case 0xbc:
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if (s->fifocnt == 0) {
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fprintf(stderr, "pl181: Unexpected FIFO write\n");
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} else {
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s->fifocnt--;
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pl181_fifo_push(s, value);
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pl181_fifo_run(s);
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}
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break;
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default:
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cpu_abort (cpu_single_env, "pl181_write: Bad offset %x\n", offset);
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}
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pl181_update(s);
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}
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static CPUReadMemoryFunc *pl181_readfn[] = {
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pl181_read,
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pl181_read,
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pl181_read
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};
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static CPUWriteMemoryFunc *pl181_writefn[] = {
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pl181_write,
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pl181_write,
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pl181_write
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};
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static void pl181_reset(void *opaque)
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{
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pl181_state *s = (pl181_state *)opaque;
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s->power = 0;
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s->cmdarg = 0;
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s->cmd = 0;
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s->datatimer = 0;
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s->datalength = 0;
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s->respcmd = 0;
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s->response[0] = 0;
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s->response[1] = 0;
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s->response[2] = 0;
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s->response[3] = 0;
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s->datatimer = 0;
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s->datalength = 0;
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s->datactrl = 0;
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s->datacnt = 0;
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s->status = 0;
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s->mask[0] = 0;
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s->mask[1] = 0;
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s->fifocnt = 0;
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}
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void pl181_init(uint32_t base, BlockDriverState *bd,
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qemu_irq irq0, qemu_irq irq1)
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{
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int iomemtype;
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pl181_state *s;
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s = (pl181_state *)qemu_mallocz(sizeof(pl181_state));
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iomemtype = cpu_register_io_memory(0, pl181_readfn,
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pl181_writefn, s);
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cpu_register_physical_memory(base, 0x00000fff, iomemtype);
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s->base = base;
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s->card = sd_init(bd);
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s->irq[0] = irq0;
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s->irq[1] = irq1;
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qemu_register_reset(pl181_reset, s);
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pl181_reset(s);
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/* ??? Save/restore. */
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}
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