1052 lines
30 KiB
C
1052 lines
30 KiB
C
/*
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* Intel XScale PXA255/270 LCDC emulation.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Written by Andrzej Zaborowski <balrog@zabor.org>
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*
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* This code is licensed under the GPLv2.
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*/
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#include "hw.h"
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#include "ui/console.h"
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#include "pxa.h"
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#include "ui/pixel_ops.h"
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/* FIXME: For graphic_rotate. Should probably be done in common code. */
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#include "sysemu/sysemu.h"
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#include "framebuffer.h"
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struct DMAChannel {
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uint32_t branch;
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uint8_t up;
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uint8_t palette[1024];
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uint8_t pbuffer[1024];
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void (*redraw)(PXA2xxLCDState *s, hwaddr addr,
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int *miny, int *maxy);
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uint32_t descriptor;
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uint32_t source;
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uint32_t id;
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uint32_t command;
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};
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struct PXA2xxLCDState {
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MemoryRegion *sysmem;
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MemoryRegion iomem;
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qemu_irq irq;
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int irqlevel;
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int invalidated;
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DisplayState *ds;
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drawfn *line_fn[2];
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int dest_width;
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int xres, yres;
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int pal_for;
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int transp;
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enum {
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pxa_lcdc_2bpp = 1,
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pxa_lcdc_4bpp = 2,
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pxa_lcdc_8bpp = 3,
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pxa_lcdc_16bpp = 4,
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pxa_lcdc_18bpp = 5,
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pxa_lcdc_18pbpp = 6,
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pxa_lcdc_19bpp = 7,
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pxa_lcdc_19pbpp = 8,
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pxa_lcdc_24bpp = 9,
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pxa_lcdc_25bpp = 10,
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} bpp;
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uint32_t control[6];
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uint32_t status[2];
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uint32_t ovl1c[2];
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uint32_t ovl2c[2];
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uint32_t ccr;
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uint32_t cmdcr;
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uint32_t trgbr;
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uint32_t tcr;
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uint32_t liidr;
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uint8_t bscntr;
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struct DMAChannel dma_ch[7];
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qemu_irq vsync_cb;
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int orientation;
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};
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typedef struct QEMU_PACKED {
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uint32_t fdaddr;
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uint32_t fsaddr;
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uint32_t fidr;
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uint32_t ldcmd;
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} PXAFrameDescriptor;
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#define LCCR0 0x000 /* LCD Controller Control register 0 */
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#define LCCR1 0x004 /* LCD Controller Control register 1 */
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#define LCCR2 0x008 /* LCD Controller Control register 2 */
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#define LCCR3 0x00c /* LCD Controller Control register 3 */
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#define LCCR4 0x010 /* LCD Controller Control register 4 */
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#define LCCR5 0x014 /* LCD Controller Control register 5 */
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#define FBR0 0x020 /* DMA Channel 0 Frame Branch register */
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#define FBR1 0x024 /* DMA Channel 1 Frame Branch register */
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#define FBR2 0x028 /* DMA Channel 2 Frame Branch register */
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#define FBR3 0x02c /* DMA Channel 3 Frame Branch register */
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#define FBR4 0x030 /* DMA Channel 4 Frame Branch register */
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#define FBR5 0x110 /* DMA Channel 5 Frame Branch register */
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#define FBR6 0x114 /* DMA Channel 6 Frame Branch register */
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#define LCSR1 0x034 /* LCD Controller Status register 1 */
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#define LCSR0 0x038 /* LCD Controller Status register 0 */
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#define LIIDR 0x03c /* LCD Controller Interrupt ID register */
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#define TRGBR 0x040 /* TMED RGB Seed register */
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#define TCR 0x044 /* TMED Control register */
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#define OVL1C1 0x050 /* Overlay 1 Control register 1 */
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#define OVL1C2 0x060 /* Overlay 1 Control register 2 */
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#define OVL2C1 0x070 /* Overlay 2 Control register 1 */
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#define OVL2C2 0x080 /* Overlay 2 Control register 2 */
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#define CCR 0x090 /* Cursor Control register */
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#define CMDCR 0x100 /* Command Control register */
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#define PRSR 0x104 /* Panel Read Status register */
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#define PXA_LCDDMA_CHANS 7
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#define DMA_FDADR 0x00 /* Frame Descriptor Address register */
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#define DMA_FSADR 0x04 /* Frame Source Address register */
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#define DMA_FIDR 0x08 /* Frame ID register */
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#define DMA_LDCMD 0x0c /* Command register */
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/* LCD Buffer Strength Control register */
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#define BSCNTR 0x04000054
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/* Bitfield masks */
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#define LCCR0_ENB (1 << 0)
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#define LCCR0_CMS (1 << 1)
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#define LCCR0_SDS (1 << 2)
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#define LCCR0_LDM (1 << 3)
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#define LCCR0_SOFM0 (1 << 4)
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#define LCCR0_IUM (1 << 5)
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#define LCCR0_EOFM0 (1 << 6)
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#define LCCR0_PAS (1 << 7)
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#define LCCR0_DPD (1 << 9)
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#define LCCR0_DIS (1 << 10)
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#define LCCR0_QDM (1 << 11)
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#define LCCR0_PDD (0xff << 12)
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#define LCCR0_BSM0 (1 << 20)
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#define LCCR0_OUM (1 << 21)
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#define LCCR0_LCDT (1 << 22)
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#define LCCR0_RDSTM (1 << 23)
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#define LCCR0_CMDIM (1 << 24)
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#define LCCR0_OUC (1 << 25)
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#define LCCR0_LDDALT (1 << 26)
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#define LCCR1_PPL(x) ((x) & 0x3ff)
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#define LCCR2_LPP(x) ((x) & 0x3ff)
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#define LCCR3_API (15 << 16)
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#define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8))
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#define LCCR3_PDFOR(x) (((x) >> 30) & 3)
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#define LCCR4_K1(x) (((x) >> 0) & 7)
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#define LCCR4_K2(x) (((x) >> 3) & 7)
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#define LCCR4_K3(x) (((x) >> 6) & 7)
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#define LCCR4_PALFOR(x) (((x) >> 15) & 3)
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#define LCCR5_SOFM(ch) (1 << (ch - 1))
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#define LCCR5_EOFM(ch) (1 << (ch + 7))
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#define LCCR5_BSM(ch) (1 << (ch + 15))
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#define LCCR5_IUM(ch) (1 << (ch + 23))
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#define OVLC1_EN (1 << 31)
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#define CCR_CEN (1 << 31)
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#define FBR_BRA (1 << 0)
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#define FBR_BINT (1 << 1)
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#define FBR_SRCADDR (0xfffffff << 4)
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#define LCSR0_LDD (1 << 0)
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#define LCSR0_SOF0 (1 << 1)
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#define LCSR0_BER (1 << 2)
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#define LCSR0_ABC (1 << 3)
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#define LCSR0_IU0 (1 << 4)
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#define LCSR0_IU1 (1 << 5)
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#define LCSR0_OU (1 << 6)
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#define LCSR0_QD (1 << 7)
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#define LCSR0_EOF0 (1 << 8)
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#define LCSR0_BS0 (1 << 9)
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#define LCSR0_SINT (1 << 10)
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#define LCSR0_RDST (1 << 11)
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#define LCSR0_CMDINT (1 << 12)
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#define LCSR0_BERCH(x) (((x) & 7) << 28)
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#define LCSR1_SOF(ch) (1 << (ch - 1))
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#define LCSR1_EOF(ch) (1 << (ch + 7))
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#define LCSR1_BS(ch) (1 << (ch + 15))
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#define LCSR1_IU(ch) (1 << (ch + 23))
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#define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
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#define LDCMD_EOFINT (1 << 21)
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#define LDCMD_SOFINT (1 << 22)
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#define LDCMD_PAL (1 << 26)
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/* Route internal interrupt lines to the global IC */
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static void pxa2xx_lcdc_int_update(PXA2xxLCDState *s)
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{
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int level = 0;
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level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM);
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level |= (s->status[0] & LCSR0_SOF0) && !(s->control[0] & LCCR0_SOFM0);
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level |= (s->status[0] & LCSR0_IU0) && !(s->control[0] & LCCR0_IUM);
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level |= (s->status[0] & LCSR0_IU1) && !(s->control[5] & LCCR5_IUM(1));
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level |= (s->status[0] & LCSR0_OU) && !(s->control[0] & LCCR0_OUM);
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level |= (s->status[0] & LCSR0_QD) && !(s->control[0] & LCCR0_QDM);
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level |= (s->status[0] & LCSR0_EOF0) && !(s->control[0] & LCCR0_EOFM0);
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level |= (s->status[0] & LCSR0_BS0) && !(s->control[0] & LCCR0_BSM0);
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level |= (s->status[0] & LCSR0_RDST) && !(s->control[0] & LCCR0_RDSTM);
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level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM);
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level |= (s->status[1] & ~s->control[5]);
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qemu_set_irq(s->irq, !!level);
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s->irqlevel = level;
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}
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/* Set Branch Status interrupt high and poke associated registers */
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static inline void pxa2xx_dma_bs_set(PXA2xxLCDState *s, int ch)
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{
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int unmasked;
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if (ch == 0) {
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s->status[0] |= LCSR0_BS0;
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unmasked = !(s->control[0] & LCCR0_BSM0);
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} else {
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s->status[1] |= LCSR1_BS(ch);
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unmasked = !(s->control[5] & LCCR5_BSM(ch));
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}
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if (unmasked) {
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if (s->irqlevel)
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s->status[0] |= LCSR0_SINT;
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else
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s->liidr = s->dma_ch[ch].id;
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}
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}
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/* Set Start Of Frame Status interrupt high and poke associated registers */
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static inline void pxa2xx_dma_sof_set(PXA2xxLCDState *s, int ch)
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{
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int unmasked;
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if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
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return;
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if (ch == 0) {
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s->status[0] |= LCSR0_SOF0;
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unmasked = !(s->control[0] & LCCR0_SOFM0);
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} else {
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s->status[1] |= LCSR1_SOF(ch);
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unmasked = !(s->control[5] & LCCR5_SOFM(ch));
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}
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if (unmasked) {
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if (s->irqlevel)
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s->status[0] |= LCSR0_SINT;
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else
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s->liidr = s->dma_ch[ch].id;
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}
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}
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/* Set End Of Frame Status interrupt high and poke associated registers */
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static inline void pxa2xx_dma_eof_set(PXA2xxLCDState *s, int ch)
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{
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int unmasked;
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if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
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return;
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if (ch == 0) {
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s->status[0] |= LCSR0_EOF0;
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unmasked = !(s->control[0] & LCCR0_EOFM0);
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} else {
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s->status[1] |= LCSR1_EOF(ch);
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unmasked = !(s->control[5] & LCCR5_EOFM(ch));
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}
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if (unmasked) {
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if (s->irqlevel)
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s->status[0] |= LCSR0_SINT;
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else
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s->liidr = s->dma_ch[ch].id;
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}
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}
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/* Set Bus Error Status interrupt high and poke associated registers */
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static inline void pxa2xx_dma_ber_set(PXA2xxLCDState *s, int ch)
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{
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s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
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if (s->irqlevel)
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s->status[0] |= LCSR0_SINT;
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else
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s->liidr = s->dma_ch[ch].id;
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}
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/* Set Read Status interrupt high and poke associated registers */
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static inline void pxa2xx_dma_rdst_set(PXA2xxLCDState *s)
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{
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s->status[0] |= LCSR0_RDST;
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if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM))
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s->status[0] |= LCSR0_SINT;
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}
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/* Load new Frame Descriptors from DMA */
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static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
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{
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PXAFrameDescriptor desc;
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hwaddr descptr;
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int i;
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for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
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s->dma_ch[i].source = 0;
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if (!s->dma_ch[i].up)
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continue;
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if (s->dma_ch[i].branch & FBR_BRA) {
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descptr = s->dma_ch[i].branch & FBR_SRCADDR;
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if (s->dma_ch[i].branch & FBR_BINT)
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pxa2xx_dma_bs_set(s, i);
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s->dma_ch[i].branch &= ~FBR_BRA;
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} else
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descptr = s->dma_ch[i].descriptor;
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if (!((descptr >= PXA2XX_SDRAM_BASE && descptr +
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sizeof(desc) <= PXA2XX_SDRAM_BASE + ram_size) ||
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(descptr >= PXA2XX_INTERNAL_BASE && descptr + sizeof(desc) <=
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PXA2XX_INTERNAL_BASE + PXA2XX_INTERNAL_SIZE))) {
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continue;
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}
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cpu_physical_memory_read(descptr, (void *)&desc, sizeof(desc));
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s->dma_ch[i].descriptor = tswap32(desc.fdaddr);
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s->dma_ch[i].source = tswap32(desc.fsaddr);
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s->dma_ch[i].id = tswap32(desc.fidr);
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s->dma_ch[i].command = tswap32(desc.ldcmd);
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}
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}
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static uint64_t pxa2xx_lcdc_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
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int ch;
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switch (offset) {
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case LCCR0:
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return s->control[0];
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case LCCR1:
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return s->control[1];
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case LCCR2:
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return s->control[2];
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case LCCR3:
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return s->control[3];
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case LCCR4:
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return s->control[4];
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case LCCR5:
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return s->control[5];
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case OVL1C1:
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return s->ovl1c[0];
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case OVL1C2:
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return s->ovl1c[1];
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case OVL2C1:
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return s->ovl2c[0];
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case OVL2C2:
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return s->ovl2c[1];
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case CCR:
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return s->ccr;
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case CMDCR:
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return s->cmdcr;
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case TRGBR:
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return s->trgbr;
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case TCR:
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return s->tcr;
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case 0x200 ... 0x1000: /* DMA per-channel registers */
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ch = (offset - 0x200) >> 4;
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if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
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goto fail;
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switch (offset & 0xf) {
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case DMA_FDADR:
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return s->dma_ch[ch].descriptor;
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case DMA_FSADR:
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return s->dma_ch[ch].source;
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case DMA_FIDR:
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return s->dma_ch[ch].id;
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case DMA_LDCMD:
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return s->dma_ch[ch].command;
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default:
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goto fail;
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}
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case FBR0:
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return s->dma_ch[0].branch;
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case FBR1:
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return s->dma_ch[1].branch;
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case FBR2:
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return s->dma_ch[2].branch;
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case FBR3:
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return s->dma_ch[3].branch;
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case FBR4:
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return s->dma_ch[4].branch;
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case FBR5:
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return s->dma_ch[5].branch;
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case FBR6:
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return s->dma_ch[6].branch;
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case BSCNTR:
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return s->bscntr;
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case PRSR:
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return 0;
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case LCSR0:
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return s->status[0];
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case LCSR1:
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return s->status[1];
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case LIIDR:
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return s->liidr;
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default:
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fail:
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hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
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}
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return 0;
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}
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static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
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int ch;
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switch (offset) {
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case LCCR0:
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/* ACK Quick Disable done */
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if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB))
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s->status[0] |= LCSR0_QD;
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if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT))
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printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
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if ((s->control[3] & LCCR3_API) &&
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(value & LCCR0_ENB) && !(value & LCCR0_LCDT))
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s->status[0] |= LCSR0_ABC;
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s->control[0] = value & 0x07ffffff;
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pxa2xx_lcdc_int_update(s);
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s->dma_ch[0].up = !!(value & LCCR0_ENB);
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s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS);
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break;
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case LCCR1:
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s->control[1] = value;
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break;
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case LCCR2:
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s->control[2] = value;
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break;
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case LCCR3:
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s->control[3] = value & 0xefffffff;
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s->bpp = LCCR3_BPP(value);
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break;
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case LCCR4:
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s->control[4] = value & 0x83ff81ff;
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break;
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case LCCR5:
|
|
s->control[5] = value & 0x3f3f3f3f;
|
|
break;
|
|
|
|
case OVL1C1:
|
|
if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN))
|
|
printf("%s: Overlay 1 not supported\n", __FUNCTION__);
|
|
|
|
s->ovl1c[0] = value & 0x80ffffff;
|
|
s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS);
|
|
break;
|
|
|
|
case OVL1C2:
|
|
s->ovl1c[1] = value & 0x000fffff;
|
|
break;
|
|
|
|
case OVL2C1:
|
|
if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN))
|
|
printf("%s: Overlay 2 not supported\n", __FUNCTION__);
|
|
|
|
s->ovl2c[0] = value & 0x80ffffff;
|
|
s->dma_ch[2].up = !!(value & OVLC1_EN);
|
|
s->dma_ch[3].up = !!(value & OVLC1_EN);
|
|
s->dma_ch[4].up = !!(value & OVLC1_EN);
|
|
break;
|
|
|
|
case OVL2C2:
|
|
s->ovl2c[1] = value & 0x007fffff;
|
|
break;
|
|
|
|
case CCR:
|
|
if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
|
|
printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
|
|
|
|
s->ccr = value & 0x81ffffe7;
|
|
s->dma_ch[5].up = !!(value & CCR_CEN);
|
|
break;
|
|
|
|
case CMDCR:
|
|
s->cmdcr = value & 0xff;
|
|
break;
|
|
|
|
case TRGBR:
|
|
s->trgbr = value & 0x00ffffff;
|
|
break;
|
|
|
|
case TCR:
|
|
s->tcr = value & 0x7fff;
|
|
break;
|
|
|
|
case 0x200 ... 0x1000: /* DMA per-channel registers */
|
|
ch = (offset - 0x200) >> 4;
|
|
if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
|
|
goto fail;
|
|
|
|
switch (offset & 0xf) {
|
|
case DMA_FDADR:
|
|
s->dma_ch[ch].descriptor = value & 0xfffffff0;
|
|
break;
|
|
|
|
default:
|
|
goto fail;
|
|
}
|
|
break;
|
|
|
|
case FBR0:
|
|
s->dma_ch[0].branch = value & 0xfffffff3;
|
|
break;
|
|
case FBR1:
|
|
s->dma_ch[1].branch = value & 0xfffffff3;
|
|
break;
|
|
case FBR2:
|
|
s->dma_ch[2].branch = value & 0xfffffff3;
|
|
break;
|
|
case FBR3:
|
|
s->dma_ch[3].branch = value & 0xfffffff3;
|
|
break;
|
|
case FBR4:
|
|
s->dma_ch[4].branch = value & 0xfffffff3;
|
|
break;
|
|
case FBR5:
|
|
s->dma_ch[5].branch = value & 0xfffffff3;
|
|
break;
|
|
case FBR6:
|
|
s->dma_ch[6].branch = value & 0xfffffff3;
|
|
break;
|
|
|
|
case BSCNTR:
|
|
s->bscntr = value & 0xf;
|
|
break;
|
|
|
|
case PRSR:
|
|
break;
|
|
|
|
case LCSR0:
|
|
s->status[0] &= ~(value & 0xfff);
|
|
if (value & LCSR0_BER)
|
|
s->status[0] &= ~LCSR0_BERCH(7);
|
|
break;
|
|
|
|
case LCSR1:
|
|
s->status[1] &= ~(value & 0x3e3f3f);
|
|
break;
|
|
|
|
default:
|
|
fail:
|
|
hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
|
|
}
|
|
}
|
|
|
|
static const MemoryRegionOps pxa2xx_lcdc_ops = {
|
|
.read = pxa2xx_lcdc_read,
|
|
.write = pxa2xx_lcdc_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
/* Load new palette for a given DMA channel, convert to internal format */
|
|
static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp)
|
|
{
|
|
int i, n, format, r, g, b, alpha;
|
|
uint32_t *dest;
|
|
uint8_t *src;
|
|
s->pal_for = LCCR4_PALFOR(s->control[4]);
|
|
format = s->pal_for;
|
|
|
|
switch (bpp) {
|
|
case pxa_lcdc_2bpp:
|
|
n = 4;
|
|
break;
|
|
case pxa_lcdc_4bpp:
|
|
n = 16;
|
|
break;
|
|
case pxa_lcdc_8bpp:
|
|
n = 256;
|
|
break;
|
|
default:
|
|
format = 0;
|
|
return;
|
|
}
|
|
|
|
src = (uint8_t *) s->dma_ch[ch].pbuffer;
|
|
dest = (uint32_t *) s->dma_ch[ch].palette;
|
|
alpha = r = g = b = 0;
|
|
|
|
for (i = 0; i < n; i ++) {
|
|
switch (format) {
|
|
case 0: /* 16 bpp, no transparency */
|
|
alpha = 0;
|
|
if (s->control[0] & LCCR0_CMS) {
|
|
r = g = b = *(uint16_t *) src & 0xff;
|
|
}
|
|
else {
|
|
r = (*(uint16_t *) src & 0xf800) >> 8;
|
|
g = (*(uint16_t *) src & 0x07e0) >> 3;
|
|
b = (*(uint16_t *) src & 0x001f) << 3;
|
|
}
|
|
src += 2;
|
|
break;
|
|
case 1: /* 16 bpp plus transparency */
|
|
alpha = *(uint16_t *) src & (1 << 24);
|
|
if (s->control[0] & LCCR0_CMS)
|
|
r = g = b = *(uint16_t *) src & 0xff;
|
|
else {
|
|
r = (*(uint16_t *) src & 0xf800) >> 8;
|
|
g = (*(uint16_t *) src & 0x07e0) >> 3;
|
|
b = (*(uint16_t *) src & 0x001f) << 3;
|
|
}
|
|
src += 2;
|
|
break;
|
|
case 2: /* 18 bpp plus transparency */
|
|
alpha = *(uint32_t *) src & (1 << 24);
|
|
if (s->control[0] & LCCR0_CMS)
|
|
r = g = b = *(uint32_t *) src & 0xff;
|
|
else {
|
|
r = (*(uint32_t *) src & 0xf80000) >> 16;
|
|
g = (*(uint32_t *) src & 0x00fc00) >> 8;
|
|
b = (*(uint32_t *) src & 0x0000f8);
|
|
}
|
|
src += 4;
|
|
break;
|
|
case 3: /* 24 bpp plus transparency */
|
|
alpha = *(uint32_t *) src & (1 << 24);
|
|
if (s->control[0] & LCCR0_CMS)
|
|
r = g = b = *(uint32_t *) src & 0xff;
|
|
else {
|
|
r = (*(uint32_t *) src & 0xff0000) >> 16;
|
|
g = (*(uint32_t *) src & 0x00ff00) >> 8;
|
|
b = (*(uint32_t *) src & 0x0000ff);
|
|
}
|
|
src += 4;
|
|
break;
|
|
}
|
|
switch (ds_get_bits_per_pixel(s->ds)) {
|
|
case 8:
|
|
*dest = rgb_to_pixel8(r, g, b) | alpha;
|
|
break;
|
|
case 15:
|
|
*dest = rgb_to_pixel15(r, g, b) | alpha;
|
|
break;
|
|
case 16:
|
|
*dest = rgb_to_pixel16(r, g, b) | alpha;
|
|
break;
|
|
case 24:
|
|
*dest = rgb_to_pixel24(r, g, b) | alpha;
|
|
break;
|
|
case 32:
|
|
*dest = rgb_to_pixel32(r, g, b) | alpha;
|
|
break;
|
|
}
|
|
dest ++;
|
|
}
|
|
}
|
|
|
|
static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s,
|
|
hwaddr addr, int *miny, int *maxy)
|
|
{
|
|
int src_width, dest_width;
|
|
drawfn fn = NULL;
|
|
if (s->dest_width)
|
|
fn = s->line_fn[s->transp][s->bpp];
|
|
if (!fn)
|
|
return;
|
|
|
|
src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
|
|
if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
|
|
src_width *= 3;
|
|
else if (s->bpp > pxa_lcdc_16bpp)
|
|
src_width *= 4;
|
|
else if (s->bpp > pxa_lcdc_8bpp)
|
|
src_width *= 2;
|
|
|
|
dest_width = s->xres * s->dest_width;
|
|
*miny = 0;
|
|
framebuffer_update_display(s->ds, s->sysmem,
|
|
addr, s->xres, s->yres,
|
|
src_width, dest_width, s->dest_width,
|
|
s->invalidated,
|
|
fn, s->dma_ch[0].palette, miny, maxy);
|
|
}
|
|
|
|
static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s,
|
|
hwaddr addr, int *miny, int *maxy)
|
|
{
|
|
int src_width, dest_width;
|
|
drawfn fn = NULL;
|
|
if (s->dest_width)
|
|
fn = s->line_fn[s->transp][s->bpp];
|
|
if (!fn)
|
|
return;
|
|
|
|
src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
|
|
if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
|
|
src_width *= 3;
|
|
else if (s->bpp > pxa_lcdc_16bpp)
|
|
src_width *= 4;
|
|
else if (s->bpp > pxa_lcdc_8bpp)
|
|
src_width *= 2;
|
|
|
|
dest_width = s->yres * s->dest_width;
|
|
*miny = 0;
|
|
framebuffer_update_display(s->ds, s->sysmem,
|
|
addr, s->xres, s->yres,
|
|
src_width, s->dest_width, -dest_width,
|
|
s->invalidated,
|
|
fn, s->dma_ch[0].palette,
|
|
miny, maxy);
|
|
}
|
|
|
|
static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s,
|
|
hwaddr addr, int *miny, int *maxy)
|
|
{
|
|
int src_width, dest_width;
|
|
drawfn fn = NULL;
|
|
if (s->dest_width) {
|
|
fn = s->line_fn[s->transp][s->bpp];
|
|
}
|
|
if (!fn) {
|
|
return;
|
|
}
|
|
|
|
src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
|
|
if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp) {
|
|
src_width *= 3;
|
|
} else if (s->bpp > pxa_lcdc_16bpp) {
|
|
src_width *= 4;
|
|
} else if (s->bpp > pxa_lcdc_8bpp) {
|
|
src_width *= 2;
|
|
}
|
|
|
|
dest_width = s->xres * s->dest_width;
|
|
*miny = 0;
|
|
framebuffer_update_display(s->ds, s->sysmem,
|
|
addr, s->xres, s->yres,
|
|
src_width, -dest_width, -s->dest_width,
|
|
s->invalidated,
|
|
fn, s->dma_ch[0].palette, miny, maxy);
|
|
}
|
|
|
|
static void pxa2xx_lcdc_dma0_redraw_rot270(PXA2xxLCDState *s,
|
|
hwaddr addr, int *miny, int *maxy)
|
|
{
|
|
int src_width, dest_width;
|
|
drawfn fn = NULL;
|
|
if (s->dest_width) {
|
|
fn = s->line_fn[s->transp][s->bpp];
|
|
}
|
|
if (!fn) {
|
|
return;
|
|
}
|
|
|
|
src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
|
|
if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp) {
|
|
src_width *= 3;
|
|
} else if (s->bpp > pxa_lcdc_16bpp) {
|
|
src_width *= 4;
|
|
} else if (s->bpp > pxa_lcdc_8bpp) {
|
|
src_width *= 2;
|
|
}
|
|
|
|
dest_width = s->yres * s->dest_width;
|
|
*miny = 0;
|
|
framebuffer_update_display(s->ds, s->sysmem,
|
|
addr, s->xres, s->yres,
|
|
src_width, -s->dest_width, dest_width,
|
|
s->invalidated,
|
|
fn, s->dma_ch[0].palette,
|
|
miny, maxy);
|
|
}
|
|
|
|
static void pxa2xx_lcdc_resize(PXA2xxLCDState *s)
|
|
{
|
|
int width, height;
|
|
if (!(s->control[0] & LCCR0_ENB))
|
|
return;
|
|
|
|
width = LCCR1_PPL(s->control[1]) + 1;
|
|
height = LCCR2_LPP(s->control[2]) + 1;
|
|
|
|
if (width != s->xres || height != s->yres) {
|
|
if (s->orientation == 90 || s->orientation == 270) {
|
|
qemu_console_resize(s->ds, height, width);
|
|
} else {
|
|
qemu_console_resize(s->ds, width, height);
|
|
}
|
|
s->invalidated = 1;
|
|
s->xres = width;
|
|
s->yres = height;
|
|
}
|
|
}
|
|
|
|
static void pxa2xx_update_display(void *opaque)
|
|
{
|
|
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
|
|
hwaddr fbptr;
|
|
int miny, maxy;
|
|
int ch;
|
|
if (!(s->control[0] & LCCR0_ENB))
|
|
return;
|
|
|
|
pxa2xx_descriptor_load(s);
|
|
|
|
pxa2xx_lcdc_resize(s);
|
|
miny = s->yres;
|
|
maxy = 0;
|
|
s->transp = s->dma_ch[2].up || s->dma_ch[3].up;
|
|
/* Note: With overlay planes the order depends on LCCR0 bit 25. */
|
|
for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++)
|
|
if (s->dma_ch[ch].up) {
|
|
if (!s->dma_ch[ch].source) {
|
|
pxa2xx_dma_ber_set(s, ch);
|
|
continue;
|
|
}
|
|
fbptr = s->dma_ch[ch].source;
|
|
if (!((fbptr >= PXA2XX_SDRAM_BASE &&
|
|
fbptr <= PXA2XX_SDRAM_BASE + ram_size) ||
|
|
(fbptr >= PXA2XX_INTERNAL_BASE &&
|
|
fbptr <= PXA2XX_INTERNAL_BASE + PXA2XX_INTERNAL_SIZE))) {
|
|
pxa2xx_dma_ber_set(s, ch);
|
|
continue;
|
|
}
|
|
|
|
if (s->dma_ch[ch].command & LDCMD_PAL) {
|
|
cpu_physical_memory_read(fbptr, s->dma_ch[ch].pbuffer,
|
|
MAX(LDCMD_LENGTH(s->dma_ch[ch].command),
|
|
sizeof(s->dma_ch[ch].pbuffer)));
|
|
pxa2xx_palette_parse(s, ch, s->bpp);
|
|
} else {
|
|
/* Do we need to reparse palette */
|
|
if (LCCR4_PALFOR(s->control[4]) != s->pal_for)
|
|
pxa2xx_palette_parse(s, ch, s->bpp);
|
|
|
|
/* ACK frame start */
|
|
pxa2xx_dma_sof_set(s, ch);
|
|
|
|
s->dma_ch[ch].redraw(s, fbptr, &miny, &maxy);
|
|
s->invalidated = 0;
|
|
|
|
/* ACK frame completed */
|
|
pxa2xx_dma_eof_set(s, ch);
|
|
}
|
|
}
|
|
|
|
if (s->control[0] & LCCR0_DIS) {
|
|
/* ACK last frame completed */
|
|
s->control[0] &= ~LCCR0_ENB;
|
|
s->status[0] |= LCSR0_LDD;
|
|
}
|
|
|
|
if (miny >= 0) {
|
|
switch (s->orientation) {
|
|
case 0:
|
|
dpy_gfx_update(s->ds, 0, miny, s->xres, maxy - miny + 1);
|
|
break;
|
|
case 90:
|
|
dpy_gfx_update(s->ds, miny, 0, maxy - miny + 1, s->xres);
|
|
break;
|
|
case 180:
|
|
maxy = s->yres - maxy - 1;
|
|
miny = s->yres - miny - 1;
|
|
dpy_gfx_update(s->ds, 0, maxy, s->xres, miny - maxy + 1);
|
|
break;
|
|
case 270:
|
|
maxy = s->yres - maxy - 1;
|
|
miny = s->yres - miny - 1;
|
|
dpy_gfx_update(s->ds, maxy, 0, miny - maxy + 1, s->xres);
|
|
break;
|
|
}
|
|
}
|
|
pxa2xx_lcdc_int_update(s);
|
|
|
|
qemu_irq_raise(s->vsync_cb);
|
|
}
|
|
|
|
static void pxa2xx_invalidate_display(void *opaque)
|
|
{
|
|
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
|
|
s->invalidated = 1;
|
|
}
|
|
|
|
static void pxa2xx_lcdc_orientation(void *opaque, int angle)
|
|
{
|
|
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
|
|
|
|
switch (angle) {
|
|
case 0:
|
|
s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot0;
|
|
break;
|
|
case 90:
|
|
s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot90;
|
|
break;
|
|
case 180:
|
|
s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot180;
|
|
break;
|
|
case 270:
|
|
s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot270;
|
|
break;
|
|
}
|
|
|
|
s->orientation = angle;
|
|
s->xres = s->yres = -1;
|
|
pxa2xx_lcdc_resize(s);
|
|
}
|
|
|
|
static const VMStateDescription vmstate_dma_channel = {
|
|
.name = "dma_channel",
|
|
.version_id = 0,
|
|
.minimum_version_id = 0,
|
|
.minimum_version_id_old = 0,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32(branch, struct DMAChannel),
|
|
VMSTATE_UINT8(up, struct DMAChannel),
|
|
VMSTATE_BUFFER(pbuffer, struct DMAChannel),
|
|
VMSTATE_UINT32(descriptor, struct DMAChannel),
|
|
VMSTATE_UINT32(source, struct DMAChannel),
|
|
VMSTATE_UINT32(id, struct DMAChannel),
|
|
VMSTATE_UINT32(command, struct DMAChannel),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static int pxa2xx_lcdc_post_load(void *opaque, int version_id)
|
|
{
|
|
PXA2xxLCDState *s = opaque;
|
|
|
|
s->bpp = LCCR3_BPP(s->control[3]);
|
|
s->xres = s->yres = s->pal_for = -1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_pxa2xx_lcdc = {
|
|
.name = "pxa2xx_lcdc",
|
|
.version_id = 0,
|
|
.minimum_version_id = 0,
|
|
.minimum_version_id_old = 0,
|
|
.post_load = pxa2xx_lcdc_post_load,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_INT32(irqlevel, PXA2xxLCDState),
|
|
VMSTATE_INT32(transp, PXA2xxLCDState),
|
|
VMSTATE_UINT32_ARRAY(control, PXA2xxLCDState, 6),
|
|
VMSTATE_UINT32_ARRAY(status, PXA2xxLCDState, 2),
|
|
VMSTATE_UINT32_ARRAY(ovl1c, PXA2xxLCDState, 2),
|
|
VMSTATE_UINT32_ARRAY(ovl2c, PXA2xxLCDState, 2),
|
|
VMSTATE_UINT32(ccr, PXA2xxLCDState),
|
|
VMSTATE_UINT32(cmdcr, PXA2xxLCDState),
|
|
VMSTATE_UINT32(trgbr, PXA2xxLCDState),
|
|
VMSTATE_UINT32(tcr, PXA2xxLCDState),
|
|
VMSTATE_UINT32(liidr, PXA2xxLCDState),
|
|
VMSTATE_UINT8(bscntr, PXA2xxLCDState),
|
|
VMSTATE_STRUCT_ARRAY(dma_ch, PXA2xxLCDState, 7, 0,
|
|
vmstate_dma_channel, struct DMAChannel),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
#define BITS 8
|
|
#include "pxa2xx_template.h"
|
|
#define BITS 15
|
|
#include "pxa2xx_template.h"
|
|
#define BITS 16
|
|
#include "pxa2xx_template.h"
|
|
#define BITS 24
|
|
#include "pxa2xx_template.h"
|
|
#define BITS 32
|
|
#include "pxa2xx_template.h"
|
|
|
|
PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
|
|
hwaddr base, qemu_irq irq)
|
|
{
|
|
PXA2xxLCDState *s;
|
|
|
|
s = (PXA2xxLCDState *) g_malloc0(sizeof(PXA2xxLCDState));
|
|
s->invalidated = 1;
|
|
s->irq = irq;
|
|
s->sysmem = sysmem;
|
|
|
|
pxa2xx_lcdc_orientation(s, graphic_rotate);
|
|
|
|
memory_region_init_io(&s->iomem, &pxa2xx_lcdc_ops, s,
|
|
"pxa2xx-lcd-controller", 0x00100000);
|
|
memory_region_add_subregion(sysmem, base, &s->iomem);
|
|
|
|
s->ds = graphic_console_init(pxa2xx_update_display,
|
|
pxa2xx_invalidate_display,
|
|
NULL, NULL, s);
|
|
|
|
switch (ds_get_bits_per_pixel(s->ds)) {
|
|
case 0:
|
|
s->dest_width = 0;
|
|
break;
|
|
case 8:
|
|
s->line_fn[0] = pxa2xx_draw_fn_8;
|
|
s->line_fn[1] = pxa2xx_draw_fn_8t;
|
|
s->dest_width = 1;
|
|
break;
|
|
case 15:
|
|
s->line_fn[0] = pxa2xx_draw_fn_15;
|
|
s->line_fn[1] = pxa2xx_draw_fn_15t;
|
|
s->dest_width = 2;
|
|
break;
|
|
case 16:
|
|
s->line_fn[0] = pxa2xx_draw_fn_16;
|
|
s->line_fn[1] = pxa2xx_draw_fn_16t;
|
|
s->dest_width = 2;
|
|
break;
|
|
case 24:
|
|
s->line_fn[0] = pxa2xx_draw_fn_24;
|
|
s->line_fn[1] = pxa2xx_draw_fn_24t;
|
|
s->dest_width = 3;
|
|
break;
|
|
case 32:
|
|
s->line_fn[0] = pxa2xx_draw_fn_32;
|
|
s->line_fn[1] = pxa2xx_draw_fn_32t;
|
|
s->dest_width = 4;
|
|
break;
|
|
default:
|
|
fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
|
|
exit(1);
|
|
}
|
|
|
|
vmstate_register(NULL, 0, &vmstate_pxa2xx_lcdc, s);
|
|
|
|
return s;
|
|
}
|
|
|
|
void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler)
|
|
{
|
|
s->vsync_cb = handler;
|
|
}
|