5927ed846a
With the latest clang, we have the following warning:
/home/pranith/devops/code/qemu/include/qemu/seqlock.h:62:21: warning: passing 'typeof (*&sl->sequence) *' (aka 'const unsigned int *') to parameter of type 'unsigned int *' discards qualifiers [-Wincompatible-pointer-types-discards-qualifiers]
return unlikely(atomic_read(&sl->sequence) != start);
^~~~~~~~~~~~~~~~~~~~~~~~~~
/home/pranith/devops/code/qemu/include/qemu/atomic.h:58:25: note: expanded from macro 'atomic_read'
__atomic_load(ptr, &_val, __ATOMIC_RELAXED); \
^~~~~
Stripping const is a bit tricky due to promotions, but it is doable
with either C11 _Generic or GCC extensions. Use the latter.
Reported-by: Pranith Kumar <bobby.prani@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
[pranith: Add conversion for bool type]
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
410 lines
17 KiB
C
410 lines
17 KiB
C
/*
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* Simple interface for atomic operations.
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*
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* Copyright (C) 2013 Red Hat, Inc.
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*
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* Author: Paolo Bonzini <pbonzini@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* See docs/atomics.txt for discussion about the guarantees each
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* atomic primitive is meant to provide.
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*/
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#ifndef QEMU_ATOMIC_H
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#define QEMU_ATOMIC_H
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/* Compiler barrier */
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#define barrier() ({ asm volatile("" ::: "memory"); (void)0; })
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/* The variable that receives the old value of an atomically-accessed
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* variable must be non-qualified, because atomic builtins return values
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* through a pointer-type argument as in __atomic_load(&var, &old, MODEL).
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*
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* This macro has to handle types smaller than int manually, because of
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* implicit promotion. int and larger types, as well as pointers, can be
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* converted to a non-qualified type just by applying a binary operator.
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*/
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#define typeof_strip_qual(expr) \
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typeof( \
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__builtin_choose_expr( \
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__builtin_types_compatible_p(typeof(expr), bool) || \
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__builtin_types_compatible_p(typeof(expr), const bool) || \
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__builtin_types_compatible_p(typeof(expr), volatile bool) || \
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__builtin_types_compatible_p(typeof(expr), const volatile bool), \
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(bool)1, \
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__builtin_choose_expr( \
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__builtin_types_compatible_p(typeof(expr), signed char) || \
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__builtin_types_compatible_p(typeof(expr), const signed char) || \
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__builtin_types_compatible_p(typeof(expr), volatile signed char) || \
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__builtin_types_compatible_p(typeof(expr), const volatile signed char), \
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(signed char)1, \
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__builtin_choose_expr( \
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__builtin_types_compatible_p(typeof(expr), unsigned char) || \
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__builtin_types_compatible_p(typeof(expr), const unsigned char) || \
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__builtin_types_compatible_p(typeof(expr), volatile unsigned char) || \
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__builtin_types_compatible_p(typeof(expr), const volatile unsigned char), \
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(unsigned char)1, \
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__builtin_choose_expr( \
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__builtin_types_compatible_p(typeof(expr), signed short) || \
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__builtin_types_compatible_p(typeof(expr), const signed short) || \
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__builtin_types_compatible_p(typeof(expr), volatile signed short) || \
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__builtin_types_compatible_p(typeof(expr), const volatile signed short), \
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(signed short)1, \
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__builtin_choose_expr( \
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__builtin_types_compatible_p(typeof(expr), unsigned short) || \
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__builtin_types_compatible_p(typeof(expr), const unsigned short) || \
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__builtin_types_compatible_p(typeof(expr), volatile unsigned short) || \
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__builtin_types_compatible_p(typeof(expr), const volatile unsigned short), \
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(unsigned short)1, \
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(expr)+0))))))
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#ifdef __ATOMIC_RELAXED
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/* For C11 atomic ops */
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/* Manual memory barriers
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*
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*__atomic_thread_fence does not include a compiler barrier; instead,
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* the barrier is part of __atomic_load/__atomic_store's "volatile-like"
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* semantics. If smp_wmb() is a no-op, absence of the barrier means that
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* the compiler is free to reorder stores on each side of the barrier.
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* Add one here, and similarly in smp_rmb() and smp_read_barrier_depends().
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*/
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#define smp_mb() ({ barrier(); __atomic_thread_fence(__ATOMIC_SEQ_CST); barrier(); })
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#define smp_wmb() ({ barrier(); __atomic_thread_fence(__ATOMIC_RELEASE); barrier(); })
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#define smp_rmb() ({ barrier(); __atomic_thread_fence(__ATOMIC_ACQUIRE); barrier(); })
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/* Most compilers currently treat consume and acquire the same, but really
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* no processors except Alpha need a barrier here. Leave it in if
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* using Thread Sanitizer to avoid warnings, otherwise optimize it away.
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*/
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#if defined(__SANITIZE_THREAD__)
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#define smp_read_barrier_depends() ({ barrier(); __atomic_thread_fence(__ATOMIC_CONSUME); barrier(); })
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#elsif defined(__alpha__)
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#define smp_read_barrier_depends() asm volatile("mb":::"memory")
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#else
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#define smp_read_barrier_depends() barrier()
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#endif
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/* Weak atomic operations prevent the compiler moving other
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* loads/stores past the atomic operation load/store. However there is
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* no explicit memory barrier for the processor.
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*/
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#define atomic_read(ptr) \
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({ \
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
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typeof_strip_qual(*ptr) _val; \
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__atomic_load(ptr, &_val, __ATOMIC_RELAXED); \
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_val; \
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})
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#define atomic_set(ptr, i) do { \
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
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typeof(*ptr) _val = (i); \
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__atomic_store(ptr, &_val, __ATOMIC_RELAXED); \
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} while(0)
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/* See above: most compilers currently treat consume and acquire the
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* same, but this slows down atomic_rcu_read unnecessarily.
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*/
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#ifdef __SANITIZE_THREAD__
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#define atomic_rcu_read__nocheck(ptr, valptr) \
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__atomic_load(ptr, valptr, __ATOMIC_CONSUME);
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#else
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#define atomic_rcu_read__nocheck(ptr, valptr) \
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__atomic_load(ptr, valptr, __ATOMIC_RELAXED); \
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smp_read_barrier_depends();
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#endif
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#define atomic_rcu_read(ptr) \
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({ \
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
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typeof_strip_qual(*ptr) _val; \
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atomic_rcu_read__nocheck(ptr, &_val); \
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_val; \
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})
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#define atomic_rcu_set(ptr, i) do { \
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
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typeof(*ptr) _val = (i); \
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__atomic_store(ptr, &_val, __ATOMIC_RELEASE); \
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} while(0)
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/* atomic_mb_read/set semantics map Java volatile variables. They are
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* less expensive on some platforms (notably POWER & ARMv7) than fully
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* sequentially consistent operations.
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*
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* As long as they are used as paired operations they are safe to
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* use. See docs/atomic.txt for more discussion.
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*/
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#if defined(_ARCH_PPC)
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#define atomic_mb_read(ptr) \
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({ \
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
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typeof_strip_qual(*ptr) _val; \
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__atomic_load(ptr, &_val, __ATOMIC_RELAXED); \
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smp_rmb(); \
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_val; \
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})
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#define atomic_mb_set(ptr, i) do { \
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
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typeof(*ptr) _val = (i); \
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smp_wmb(); \
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__atomic_store(ptr, &_val, __ATOMIC_RELAXED); \
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smp_mb(); \
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} while(0)
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#else
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#define atomic_mb_read(ptr) \
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({ \
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
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typeof_strip_qual(*ptr) _val; \
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__atomic_load(ptr, &_val, __ATOMIC_SEQ_CST); \
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_val; \
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})
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#define atomic_mb_set(ptr, i) do { \
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
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typeof(*ptr) _val = (i); \
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__atomic_store(ptr, &_val, __ATOMIC_SEQ_CST); \
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} while(0)
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#endif
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/* All the remaining operations are fully sequentially consistent */
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#define atomic_xchg(ptr, i) ({ \
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
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typeof_strip_qual(*ptr) _new = (i), _old; \
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__atomic_exchange(ptr, &_new, &_old, __ATOMIC_SEQ_CST); \
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_old; \
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})
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/* Returns the eventual value, failed or not */
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#define atomic_cmpxchg(ptr, old, new) \
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({ \
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
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typeof_strip_qual(*ptr) _old = (old), _new = (new); \
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__atomic_compare_exchange(ptr, &_old, &_new, false, \
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__ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); \
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_old; \
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})
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/* Provide shorter names for GCC atomic builtins, return old value */
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#define atomic_fetch_inc(ptr) __atomic_fetch_add(ptr, 1, __ATOMIC_SEQ_CST)
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#define atomic_fetch_dec(ptr) __atomic_fetch_sub(ptr, 1, __ATOMIC_SEQ_CST)
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#define atomic_fetch_add(ptr, n) __atomic_fetch_add(ptr, n, __ATOMIC_SEQ_CST)
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#define atomic_fetch_sub(ptr, n) __atomic_fetch_sub(ptr, n, __ATOMIC_SEQ_CST)
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#define atomic_fetch_and(ptr, n) __atomic_fetch_and(ptr, n, __ATOMIC_SEQ_CST)
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#define atomic_fetch_or(ptr, n) __atomic_fetch_or(ptr, n, __ATOMIC_SEQ_CST)
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/* And even shorter names that return void. */
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#define atomic_inc(ptr) ((void) __atomic_fetch_add(ptr, 1, __ATOMIC_SEQ_CST))
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#define atomic_dec(ptr) ((void) __atomic_fetch_sub(ptr, 1, __ATOMIC_SEQ_CST))
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#define atomic_add(ptr, n) ((void) __atomic_fetch_add(ptr, n, __ATOMIC_SEQ_CST))
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#define atomic_sub(ptr, n) ((void) __atomic_fetch_sub(ptr, n, __ATOMIC_SEQ_CST))
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#define atomic_and(ptr, n) ((void) __atomic_fetch_and(ptr, n, __ATOMIC_SEQ_CST))
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#define atomic_or(ptr, n) ((void) __atomic_fetch_or(ptr, n, __ATOMIC_SEQ_CST))
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#else /* __ATOMIC_RELAXED */
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/*
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* We use GCC builtin if it's available, as that can use mfence on
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* 32-bit as well, e.g. if built with -march=pentium-m. However, on
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* i386 the spec is buggy, and the implementation followed it until
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* 4.3 (http://gcc.gnu.org/bugzilla/show_bug.cgi?id=36793).
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*/
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#if defined(__i386__) || defined(__x86_64__)
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#if !QEMU_GNUC_PREREQ(4, 4)
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#if defined __x86_64__
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#define smp_mb() ({ asm volatile("mfence" ::: "memory"); (void)0; })
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#else
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#define smp_mb() ({ asm volatile("lock; addl $0,0(%%esp) " ::: "memory"); (void)0; })
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#endif
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#endif
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#endif
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#ifdef __alpha__
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#define smp_read_barrier_depends() asm volatile("mb":::"memory")
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#endif
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#if defined(__i386__) || defined(__x86_64__) || defined(__s390x__)
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/*
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* Because of the strongly ordered storage model, wmb() and rmb() are nops
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* here (a compiler barrier only). QEMU doesn't do accesses to write-combining
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* qemu memory or non-temporal load/stores from C code.
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*/
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#define smp_wmb() barrier()
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#define smp_rmb() barrier()
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/*
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* __sync_lock_test_and_set() is documented to be an acquire barrier only,
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* but it is a full barrier at the hardware level. Add a compiler barrier
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* to make it a full barrier also at the compiler level.
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*/
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#define atomic_xchg(ptr, i) (barrier(), __sync_lock_test_and_set(ptr, i))
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/*
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* Load/store with Java volatile semantics.
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*/
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#define atomic_mb_set(ptr, i) ((void)atomic_xchg(ptr, i))
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#elif defined(_ARCH_PPC)
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/*
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* We use an eieio() for wmb() on powerpc. This assumes we don't
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* need to order cacheable and non-cacheable stores with respect to
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* each other.
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*
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* smp_mb has the same problem as on x86 for not-very-new GCC
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* (http://patchwork.ozlabs.org/patch/126184/, Nov 2011).
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*/
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#define smp_wmb() ({ asm volatile("eieio" ::: "memory"); (void)0; })
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#if defined(__powerpc64__)
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#define smp_rmb() ({ asm volatile("lwsync" ::: "memory"); (void)0; })
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#else
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#define smp_rmb() ({ asm volatile("sync" ::: "memory"); (void)0; })
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#endif
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#define smp_mb() ({ asm volatile("sync" ::: "memory"); (void)0; })
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#endif /* _ARCH_PPC */
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/*
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* For (host) platforms we don't have explicit barrier definitions
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* for, we use the gcc __sync_synchronize() primitive to generate a
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* full barrier. This should be safe on all platforms, though it may
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* be overkill for smp_wmb() and smp_rmb().
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*/
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#ifndef smp_mb
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#define smp_mb() __sync_synchronize()
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#endif
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#ifndef smp_wmb
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#define smp_wmb() __sync_synchronize()
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#endif
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#ifndef smp_rmb
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#define smp_rmb() __sync_synchronize()
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#endif
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#ifndef smp_read_barrier_depends
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#define smp_read_barrier_depends() barrier()
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#endif
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/* These will only be atomic if the processor does the fetch or store
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* in a single issue memory operation
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*/
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#define atomic_read(ptr) (*(__typeof__(*ptr) volatile*) (ptr))
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#define atomic_set(ptr, i) ((*(__typeof__(*ptr) volatile*) (ptr)) = (i))
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/**
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* atomic_rcu_read - reads a RCU-protected pointer to a local variable
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* into a RCU read-side critical section. The pointer can later be safely
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* dereferenced within the critical section.
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*
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* This ensures that the pointer copy is invariant thorough the whole critical
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* section.
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*
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* Inserts memory barriers on architectures that require them (currently only
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* Alpha) and documents which pointers are protected by RCU.
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*
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* atomic_rcu_read also includes a compiler barrier to ensure that
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* value-speculative optimizations (e.g. VSS: Value Speculation
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* Scheduling) does not perform the data read before the pointer read
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* by speculating the value of the pointer.
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*
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* Should match atomic_rcu_set(), atomic_xchg(), atomic_cmpxchg().
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*/
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#define atomic_rcu_read(ptr) ({ \
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typeof(*ptr) _val = atomic_read(ptr); \
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smp_read_barrier_depends(); \
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_val; \
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})
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/**
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* atomic_rcu_set - assigns (publicizes) a pointer to a new data structure
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* meant to be read by RCU read-side critical sections.
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*
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* Documents which pointers will be dereferenced by RCU read-side critical
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* sections and adds the required memory barriers on architectures requiring
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* them. It also makes sure the compiler does not reorder code initializing the
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* data structure before its publication.
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*
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* Should match atomic_rcu_read().
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*/
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#define atomic_rcu_set(ptr, i) do { \
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smp_wmb(); \
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atomic_set(ptr, i); \
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} while (0)
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/* These have the same semantics as Java volatile variables.
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* See http://gee.cs.oswego.edu/dl/jmm/cookbook.html:
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* "1. Issue a StoreStore barrier (wmb) before each volatile store."
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* 2. Issue a StoreLoad barrier after each volatile store.
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* Note that you could instead issue one before each volatile load, but
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* this would be slower for typical programs using volatiles in which
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* reads greatly outnumber writes. Alternatively, if available, you
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* can implement volatile store as an atomic instruction (for example
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* XCHG on x86) and omit the barrier. This may be more efficient if
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* atomic instructions are cheaper than StoreLoad barriers.
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* 3. Issue LoadLoad and LoadStore barriers after each volatile load."
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*
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* If you prefer to think in terms of "pairing" of memory barriers,
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* an atomic_mb_read pairs with an atomic_mb_set.
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*
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* And for the few ia64 lovers that exist, an atomic_mb_read is a ld.acq,
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* while an atomic_mb_set is a st.rel followed by a memory barrier.
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*
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* These are a bit weaker than __atomic_load/store with __ATOMIC_SEQ_CST
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* (see docs/atomics.txt), and I'm not sure that __ATOMIC_ACQ_REL is enough.
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* Just always use the barriers manually by the rules above.
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*/
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#define atomic_mb_read(ptr) ({ \
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typeof(*ptr) _val = atomic_read(ptr); \
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smp_rmb(); \
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_val; \
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})
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#ifndef atomic_mb_set
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#define atomic_mb_set(ptr, i) do { \
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smp_wmb(); \
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atomic_set(ptr, i); \
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smp_mb(); \
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} while (0)
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#endif
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#ifndef atomic_xchg
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#if defined(__clang__)
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#define atomic_xchg(ptr, i) __sync_swap(ptr, i)
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#else
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/* __sync_lock_test_and_set() is documented to be an acquire barrier only. */
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#define atomic_xchg(ptr, i) (smp_mb(), __sync_lock_test_and_set(ptr, i))
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#endif
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#endif
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/* Provide shorter names for GCC atomic builtins. */
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#define atomic_fetch_inc(ptr) __sync_fetch_and_add(ptr, 1)
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#define atomic_fetch_dec(ptr) __sync_fetch_and_add(ptr, -1)
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#define atomic_fetch_add __sync_fetch_and_add
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#define atomic_fetch_sub __sync_fetch_and_sub
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#define atomic_fetch_and __sync_fetch_and_and
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#define atomic_fetch_or __sync_fetch_and_or
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#define atomic_cmpxchg __sync_val_compare_and_swap
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/* And even shorter names that return void. */
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#define atomic_inc(ptr) ((void) __sync_fetch_and_add(ptr, 1))
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#define atomic_dec(ptr) ((void) __sync_fetch_and_add(ptr, -1))
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#define atomic_add(ptr, n) ((void) __sync_fetch_and_add(ptr, n))
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#define atomic_sub(ptr, n) ((void) __sync_fetch_and_sub(ptr, n))
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#define atomic_and(ptr, n) ((void) __sync_fetch_and_and(ptr, n))
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#define atomic_or(ptr, n) ((void) __sync_fetch_and_or(ptr, n))
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#endif /* __ATOMIC_RELAXED */
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#endif /* QEMU_ATOMIC_H */
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