Leonid Bloch 3b27430177 e1000: Implementing various counters
This implements the following Statistic registers (various counters)
according to Intel's specs:

TSCTC  GOTCL  GOTCH  GORCL  GORCH  MPRC   BPRC   RUC    ROC
BPTC   MPTC   PTC... PRC...

PLEASE NOTE: these registers will not be active, nor will migrate, until
a compatibility flag will be set (in the next patch in this series).

Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2015-11-12 15:26:54 +08:00
..
2015-09-11 10:45:43 +03:00
2015-11-12 15:26:54 +08:00
2015-07-27 14:12:18 +01:00
2015-10-27 15:59:46 +00:00
2015-07-20 17:47:24 +01:00
2015-07-27 14:12:18 +01:00
2015-09-07 10:39:30 +01:00
2015-09-02 14:51:07 +01:00
2015-09-02 14:51:07 +01:00
2015-07-27 14:12:18 +01:00
2015-09-25 14:53:50 +02:00
2015-07-27 14:12:18 +01:00
2015-09-25 14:53:29 +02:00