Max Filippov 4e41d2f583 target-xtensa: implement CACHEATTR SR
In XEA1, the Options for Memory Protection and Translation and the
corresponding TLB management instructions are not available. Instead,
functionality similar to the Region Protection Option is available
through the cache attribute register. See ISA, A.2.14 for details.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Read the documentation in qemu-doc.html or on http://wiki.qemu.org

- QEMU team
Description
A fork of QEMU-Nyx which is better suited for my bachelors thesis
Readme 154 MiB
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