It's reverse of apicid_from_topo_ids() and will be used in follow up patches to fill in data structures for query-hotpluggable-cpus and for user friendly error reporting. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
		
			
				
	
	
		
			149 lines
		
	
	
		
			5.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			149 lines
		
	
	
		
			5.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 *  x86 CPU topology data structures and functions
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 *
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 *  Copyright (c) 2012 Red Hat Inc.
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#ifndef HW_I386_TOPOLOGY_H
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#define HW_I386_TOPOLOGY_H
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/* This file implements the APIC-ID-based CPU topology enumeration logic,
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 * documented at the following document:
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 *   Intel® 64 Architecture Processor Topology Enumeration
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 *   http://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/
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 *
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 * This code should be compatible with AMD's "Extended Method" described at:
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 *   AMD CPUID Specification (Publication #25481)
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 *   Section 3: Multiple Core Calcuation
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 * as long as:
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 *  nr_threads is set to 1;
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 *  OFFSET_IDX is assumed to be 0;
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 *  CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_width().
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 */
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#include "qemu/bitops.h"
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/* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support
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 */
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typedef uint32_t apic_id_t;
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typedef struct X86CPUTopoInfo {
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    unsigned pkg_id;
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    unsigned core_id;
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    unsigned smt_id;
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} X86CPUTopoInfo;
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/* Return the bit width needed for 'count' IDs
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 */
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static unsigned apicid_bitwidth_for_count(unsigned count)
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{
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    g_assert(count >= 1);
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    count -= 1;
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    return count ? 32 - clz32(count) : 0;
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}
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/* Bit width of the SMT_ID (thread ID) field on the APIC ID
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 */
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static inline unsigned apicid_smt_width(unsigned nr_cores, unsigned nr_threads)
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{
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    return apicid_bitwidth_for_count(nr_threads);
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}
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/* Bit width of the Core_ID field
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 */
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static inline unsigned apicid_core_width(unsigned nr_cores, unsigned nr_threads)
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{
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    return apicid_bitwidth_for_count(nr_cores);
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}
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/* Bit offset of the Core_ID field
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 */
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static inline unsigned apicid_core_offset(unsigned nr_cores,
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                                          unsigned nr_threads)
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{
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    return apicid_smt_width(nr_cores, nr_threads);
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}
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/* Bit offset of the Pkg_ID (socket ID) field
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 */
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static inline unsigned apicid_pkg_offset(unsigned nr_cores, unsigned nr_threads)
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{
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    return apicid_core_offset(nr_cores, nr_threads) +
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           apicid_core_width(nr_cores, nr_threads);
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}
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/* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
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 *
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 * The caller must make sure core_id < nr_cores and smt_id < nr_threads.
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 */
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static inline apic_id_t apicid_from_topo_ids(unsigned nr_cores,
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                                             unsigned nr_threads,
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                                             const X86CPUTopoInfo *topo)
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{
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    return (topo->pkg_id  << apicid_pkg_offset(nr_cores, nr_threads)) |
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           (topo->core_id << apicid_core_offset(nr_cores, nr_threads)) |
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           topo->smt_id;
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}
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/* Calculate thread/core/package IDs for a specific topology,
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 * based on (contiguous) CPU index
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 */
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static inline void x86_topo_ids_from_idx(unsigned nr_cores,
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                                         unsigned nr_threads,
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                                         unsigned cpu_index,
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                                         X86CPUTopoInfo *topo)
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{
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    unsigned core_index = cpu_index / nr_threads;
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    topo->smt_id = cpu_index % nr_threads;
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    topo->core_id = core_index % nr_cores;
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    topo->pkg_id = core_index / nr_cores;
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}
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/* Calculate thread/core/package IDs for a specific topology,
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 * based on APIC ID
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 */
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static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
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                                            unsigned nr_cores,
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                                            unsigned nr_threads,
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                                            X86CPUTopoInfo *topo)
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{
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    topo->smt_id = apicid &
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                   ~(0xFFFFFFFFUL << apicid_smt_width(nr_cores, nr_threads));
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    topo->core_id = (apicid >> apicid_core_offset(nr_cores, nr_threads)) &
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                   ~(0xFFFFFFFFUL << apicid_core_width(nr_cores, nr_threads));
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    topo->pkg_id = apicid >> apicid_pkg_offset(nr_cores, nr_threads);
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}
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/* Make APIC ID for the CPU 'cpu_index'
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 *
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 * 'cpu_index' is a sequential, contiguous ID for the CPU.
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 */
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static inline apic_id_t x86_apicid_from_cpu_idx(unsigned nr_cores,
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                                                unsigned nr_threads,
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                                                unsigned cpu_index)
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{
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    X86CPUTopoInfo topo;
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    x86_topo_ids_from_idx(nr_cores, nr_threads, cpu_index, &topo);
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    return apicid_from_topo_ids(nr_cores, nr_threads, &topo);
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}
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#endif /* HW_I386_TOPOLOGY_H */
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