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QEMU-Nyx-fork/target/riscv
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Emilio G. Cota 4b9fa0b4fa target/riscv: fetch code with translator_ld 
Signed-off-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28 15:12:38 +00:00
..
insn_trans
tcg: TCGMemOp is now accelerator independent MemOp
2019-09-03 08:30:38 -07:00
cpu_bits.h
target/riscv: Update the Hypervisor CSRs to v0.4
2019-09-17 08:42:43 -07:00
cpu_helper.c
riscv: rv32: Root page table address can be larger than 32-bit
2019-09-17 08:42:43 -07:00
cpu_user.h
Supply missing header guards
2019-06-12 13:20:21 +02:00
cpu-param.h
tcg: Split out target/arch/cpu-param.h
2019-06-10 07:03:34 -07:00
cpu.c
target/riscv: Use both register name and ABI name
2019-09-17 08:42:50 -07:00
cpu.h
target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point
2019-09-17 08:42:50 -07:00
csr.c
target/riscv: Fix mstatus dirty mask
2019-09-17 08:42:50 -07:00
fpu_helper.c
target/riscv: rationalise softfloat includes
2019-08-19 12:07:13 +01:00
gdbstub.c
gdbstub: riscv: fix the fflags registers
2019-09-17 08:42:50 -07:00
helper.h
RISC-V CPU Helpers
2018-03-07 08:30:28 +13:00
insn16-32.decode
target/riscv: Split RVC32 and RVC64 insns into separate files
2019-05-24 12:09:22 -07:00
insn16-64.decode
target/riscv: Add checks for several RVC reserved operands
2019-05-24 12:09:25 -07:00
insn16.decode
target/riscv: Add checks for several RVC reserved operands
2019-05-24 12:09:25 -07:00
insn32-64.decode
target/riscv: Convert RV64D insns to decodetree
2019-03-13 10:34:06 +01:00
insn32.decode
target/riscv: Name the argument sets for all of insn32 formats
2019-05-24 12:09:22 -07:00
instmap.h
Supply missing header guards
2019-06-12 13:20:21 +02:00
Makefile.objs
riscv: hmp: Add a command to show virtual memory mappings
2019-09-17 08:42:43 -07:00
monitor.c
riscv: hmp: Add a command to show virtual memory mappings
2019-09-17 08:42:43 -07:00
op_helper.c
target/riscv: Use env_cpu, env_archcpu
2019-06-10 07:03:42 -07:00
pmp.c
target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events
2019-09-17 08:42:42 -07:00
pmp.h
RISC-V: Check for the effective memory privilege mode during PMP checks
2019-06-23 23:44:41 -07:00
trace-events
target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events
2019-09-17 08:42:42 -07:00
translate.c
target/riscv: fetch code with translator_ld
2019-10-28 15:12:38 +00:00