26a76461f2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2018 c046a42c-6fe2-441c-8c8c-71466251a162
590 lines
16 KiB
C
590 lines
16 KiB
C
/*
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* sparc helpers
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include <signal.h>
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#include <assert.h>
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#include "cpu.h"
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#include "exec-all.h"
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//#define DEBUG_MMU
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/* Sparc MMU emulation */
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/* thread support */
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spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
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void cpu_lock(void)
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{
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spin_lock(&global_cpu_lock);
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}
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void cpu_unlock(void)
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{
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spin_unlock(&global_cpu_lock);
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}
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#if defined(CONFIG_USER_ONLY)
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int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
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int is_user, int is_softmmu)
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{
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if (rw & 2)
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env->exception_index = TT_TFAULT;
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else
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env->exception_index = TT_DFAULT;
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return 1;
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}
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#else
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#ifndef TARGET_SPARC64
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/*
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* Sparc V8 Reference MMU (SRMMU)
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*/
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static const int access_table[8][8] = {
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{ 0, 0, 0, 0, 2, 0, 3, 3 },
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{ 0, 0, 0, 0, 2, 0, 0, 0 },
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{ 2, 2, 0, 0, 0, 2, 3, 3 },
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{ 2, 2, 0, 0, 0, 2, 0, 0 },
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{ 2, 0, 2, 0, 2, 2, 3, 3 },
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{ 2, 0, 2, 0, 2, 0, 2, 0 },
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{ 2, 2, 2, 0, 2, 2, 3, 3 },
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{ 2, 2, 2, 0, 2, 2, 2, 0 }
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};
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static const int perm_table[2][8] = {
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{
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PAGE_READ,
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PAGE_READ | PAGE_WRITE,
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PAGE_READ | PAGE_EXEC,
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PAGE_READ | PAGE_WRITE | PAGE_EXEC,
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PAGE_EXEC,
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PAGE_READ | PAGE_WRITE,
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PAGE_READ | PAGE_EXEC,
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PAGE_READ | PAGE_WRITE | PAGE_EXEC
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},
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{
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PAGE_READ,
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PAGE_READ | PAGE_WRITE,
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PAGE_READ | PAGE_EXEC,
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PAGE_READ | PAGE_WRITE | PAGE_EXEC,
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PAGE_EXEC,
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PAGE_READ,
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0,
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0,
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}
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};
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int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
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int *access_index, target_ulong address, int rw,
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int is_user)
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{
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int access_perms = 0;
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target_phys_addr_t pde_ptr;
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uint32_t pde;
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target_ulong virt_addr;
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int error_code = 0, is_dirty;
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unsigned long page_offset;
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virt_addr = address & TARGET_PAGE_MASK;
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if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
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*physical = address;
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return 0;
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}
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*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
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*physical = 0xfffff000;
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/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
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/* Context base + context number */
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
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pde = ldl_phys(pde_ptr);
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/* Ctx pde */
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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return 1 << 2;
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case 2: /* L0 PTE, maybe should not happen? */
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case 3: /* Reserved */
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return 4 << 2;
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case 1: /* L0 PDE */
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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return (1 << 8) | (1 << 2);
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case 3: /* Reserved */
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return (1 << 8) | (4 << 2);
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case 1: /* L1 PDE */
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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return (2 << 8) | (1 << 2);
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case 3: /* Reserved */
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return (2 << 8) | (4 << 2);
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case 1: /* L2 PDE */
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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return (3 << 8) | (1 << 2);
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case 1: /* PDE, should not happen */
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case 3: /* Reserved */
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return (3 << 8) | (4 << 2);
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case 2: /* L3 PTE */
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virt_addr = address & TARGET_PAGE_MASK;
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page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
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}
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break;
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case 2: /* L2 PTE */
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virt_addr = address & ~0x3ffff;
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page_offset = address & 0x3ffff;
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}
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break;
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case 2: /* L1 PTE */
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virt_addr = address & ~0xffffff;
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page_offset = address & 0xffffff;
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}
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}
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/* update page modified and dirty bits */
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is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
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if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
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pde |= PG_ACCESSED_MASK;
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if (is_dirty)
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pde |= PG_MODIFIED_MASK;
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stl_phys_notdirty(pde_ptr, pde);
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}
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/* check access */
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access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
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error_code = access_table[*access_index][access_perms];
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if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
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return error_code;
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/* the page can be put in the TLB */
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*prot = perm_table[is_user][access_perms];
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if (!(pde & PG_MODIFIED_MASK)) {
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/* only set write access if already dirty... otherwise wait
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for dirty access */
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*prot &= ~PAGE_WRITE;
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}
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/* Even if large ptes, we map only one 4KB page in the cache to
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avoid filling it too fast */
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*physical = ((pde & PTE_ADDR_MASK) << 4) + page_offset;
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return error_code;
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}
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/* Perform address translation */
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int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int is_user, int is_softmmu)
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{
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target_phys_addr_t paddr;
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unsigned long vaddr;
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int error_code = 0, prot, ret = 0, access_index;
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error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
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if (error_code == 0) {
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vaddr = address & TARGET_PAGE_MASK;
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paddr &= TARGET_PAGE_MASK;
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#ifdef DEBUG_MMU
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printf("Translate at 0x%lx -> 0x%lx, vaddr 0x%lx\n", (long)address, (long)paddr, (long)vaddr);
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#endif
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ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
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return ret;
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}
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if (env->mmuregs[3]) /* Fault status register */
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env->mmuregs[3] = 1; /* overflow (not read before another fault) */
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env->mmuregs[3] |= (access_index << 5) | error_code | 2;
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env->mmuregs[4] = address; /* Fault address register */
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if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) {
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// No fault mode: if a mapping is available, just override
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// permissions. If no mapping is available, redirect accesses to
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// neverland. Fake/overridden mappings will be flushed when
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// switching to normal mode.
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vaddr = address & TARGET_PAGE_MASK;
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
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return ret;
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} else {
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if (rw & 2)
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env->exception_index = TT_TFAULT;
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else
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env->exception_index = TT_DFAULT;
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return 1;
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}
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}
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target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
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{
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target_phys_addr_t pde_ptr;
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uint32_t pde;
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/* Context base + context number */
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
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pde = ldl_phys(pde_ptr);
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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case 2: /* PTE, maybe should not happen? */
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case 3: /* Reserved */
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return 0;
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case 1: /* L1 PDE */
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if (mmulev == 3)
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return pde;
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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case 3: /* Reserved */
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return 0;
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case 2: /* L1 PTE */
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return pde;
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case 1: /* L2 PDE */
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if (mmulev == 2)
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return pde;
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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case 3: /* Reserved */
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return 0;
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case 2: /* L2 PTE */
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return pde;
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case 1: /* L3 PDE */
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if (mmulev == 1)
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return pde;
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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case 1: /* PDE, should not happen */
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case 3: /* Reserved */
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return 0;
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case 2: /* L3 PTE */
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return pde;
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}
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}
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}
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}
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return 0;
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}
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#ifdef DEBUG_MMU
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void dump_mmu(CPUState *env)
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{
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target_ulong va, va1, va2;
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unsigned int n, m, o;
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target_phys_addr_t pde_ptr, pa;
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uint32_t pde;
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printf("MMU dump:\n");
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
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pde = ldl_phys(pde_ptr);
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printf("Root ptr: " TARGET_FMT_lx ", ctx: %d\n", env->mmuregs[1] << 4, env->mmuregs[2]);
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for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
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pde_ptr = mmu_probe(env, va, 2);
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if (pde_ptr) {
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pa = cpu_get_phys_page_debug(env, va);
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printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va, pa, pde_ptr);
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for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
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pde_ptr = mmu_probe(env, va1, 1);
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if (pde_ptr) {
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pa = cpu_get_phys_page_debug(env, va1);
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printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde_ptr);
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for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
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pde_ptr = mmu_probe(env, va2, 0);
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if (pde_ptr) {
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pa = cpu_get_phys_page_debug(env, va2);
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printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PTE: " TARGET_FMT_lx "\n", va2, pa, pde_ptr);
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}
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}
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}
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}
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}
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}
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printf("MMU dump ends\n");
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}
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#endif /* DEBUG_MMU */
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#else /* !TARGET_SPARC64 */
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/*
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* UltraSparc IIi I/DMMUs
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*/
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static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot,
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int *access_index, target_ulong address, int rw,
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int is_user)
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{
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target_ulong mask;
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unsigned int i;
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if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
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*physical = address;
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*prot = PAGE_READ | PAGE_WRITE;
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return 0;
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}
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for (i = 0; i < 64; i++) {
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switch ((env->dtlb_tte[i] >> 61) & 3) {
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default:
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case 0x0: // 8k
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mask = 0xffffffffffffe000ULL;
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break;
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case 0x1: // 64k
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mask = 0xffffffffffff0000ULL;
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break;
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case 0x2: // 512k
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mask = 0xfffffffffff80000ULL;
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break;
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case 0x3: // 4M
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mask = 0xffffffffffc00000ULL;
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break;
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}
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// ctx match, vaddr match?
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if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
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(address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
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// valid, access ok?
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if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
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((env->dtlb_tte[i] & 0x4) && is_user) ||
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(!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
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if (env->dmmuregs[3]) /* Fault status register */
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env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
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env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
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env->dmmuregs[4] = address; /* Fault address register */
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env->exception_index = TT_DFAULT;
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#ifdef DEBUG_MMU
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printf("DFAULT at 0x%" PRIx64 "\n", address);
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#endif
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return 1;
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}
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*physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
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*prot = PAGE_READ;
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if (env->dtlb_tte[i] & 0x2)
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*prot |= PAGE_WRITE;
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return 0;
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}
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}
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#ifdef DEBUG_MMU
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printf("DMISS at 0x%" PRIx64 "\n", address);
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#endif
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env->exception_index = TT_DMISS;
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return 1;
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}
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static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot,
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int *access_index, target_ulong address, int rw,
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int is_user)
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{
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target_ulong mask;
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unsigned int i;
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if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
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*physical = address;
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*prot = PAGE_EXEC;
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return 0;
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}
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for (i = 0; i < 64; i++) {
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switch ((env->itlb_tte[i] >> 61) & 3) {
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default:
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case 0x0: // 8k
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mask = 0xffffffffffffe000ULL;
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break;
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case 0x1: // 64k
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mask = 0xffffffffffff0000ULL;
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break;
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case 0x2: // 512k
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mask = 0xfffffffffff80000ULL;
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break;
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case 0x3: // 4M
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mask = 0xffffffffffc00000ULL;
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break;
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}
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// ctx match, vaddr match?
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if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
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(address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
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// valid, access ok?
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if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
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((env->itlb_tte[i] & 0x4) && is_user)) {
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if (env->immuregs[3]) /* Fault status register */
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env->immuregs[3] = 2; /* overflow (not read before another fault) */
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env->immuregs[3] |= (is_user << 3) | 1;
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env->exception_index = TT_TFAULT;
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#ifdef DEBUG_MMU
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printf("TFAULT at 0x%" PRIx64 "\n", address);
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#endif
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return 1;
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}
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*physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
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*prot = PAGE_EXEC;
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return 0;
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}
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}
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#ifdef DEBUG_MMU
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printf("TMISS at 0x%" PRIx64 "\n", address);
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#endif
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env->exception_index = TT_TMISS;
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return 1;
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}
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int get_physical_address(CPUState *env, target_phys_addr_t *physical, int *prot,
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int *access_index, target_ulong address, int rw,
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int is_user)
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{
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if (rw == 2)
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return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
|
|
else
|
|
return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
|
|
}
|
|
|
|
/* Perform address translation */
|
|
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
|
|
int is_user, int is_softmmu)
|
|
{
|
|
target_ulong virt_addr, vaddr;
|
|
target_phys_addr_t paddr;
|
|
int error_code = 0, prot, ret = 0, access_index;
|
|
|
|
error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
|
|
if (error_code == 0) {
|
|
virt_addr = address & TARGET_PAGE_MASK;
|
|
vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
|
|
#ifdef DEBUG_MMU
|
|
printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr);
|
|
#endif
|
|
ret = tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
|
|
return ret;
|
|
}
|
|
// XXX
|
|
return 1;
|
|
}
|
|
|
|
#ifdef DEBUG_MMU
|
|
void dump_mmu(CPUState *env)
|
|
{
|
|
unsigned int i;
|
|
const char *mask;
|
|
|
|
printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]);
|
|
if ((env->lsu & DMMU_E) == 0) {
|
|
printf("DMMU disabled\n");
|
|
} else {
|
|
printf("DMMU dump:\n");
|
|
for (i = 0; i < 64; i++) {
|
|
switch ((env->dtlb_tte[i] >> 61) & 3) {
|
|
default:
|
|
case 0x0:
|
|
mask = " 8k";
|
|
break;
|
|
case 0x1:
|
|
mask = " 64k";
|
|
break;
|
|
case 0x2:
|
|
mask = "512k";
|
|
break;
|
|
case 0x3:
|
|
mask = " 4M";
|
|
break;
|
|
}
|
|
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
|
|
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n",
|
|
env->dtlb_tag[i] & ~0x1fffULL,
|
|
env->dtlb_tte[i] & 0x1ffffffe000ULL,
|
|
mask,
|
|
env->dtlb_tte[i] & 0x4? "priv": "user",
|
|
env->dtlb_tte[i] & 0x2? "RW": "RO",
|
|
env->dtlb_tte[i] & 0x40? "locked": "unlocked",
|
|
env->dtlb_tag[i] & 0x1fffULL);
|
|
}
|
|
}
|
|
}
|
|
if ((env->lsu & IMMU_E) == 0) {
|
|
printf("IMMU disabled\n");
|
|
} else {
|
|
printf("IMMU dump:\n");
|
|
for (i = 0; i < 64; i++) {
|
|
switch ((env->itlb_tte[i] >> 61) & 3) {
|
|
default:
|
|
case 0x0:
|
|
mask = " 8k";
|
|
break;
|
|
case 0x1:
|
|
mask = " 64k";
|
|
break;
|
|
case 0x2:
|
|
mask = "512k";
|
|
break;
|
|
case 0x3:
|
|
mask = " 4M";
|
|
break;
|
|
}
|
|
if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
|
|
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n",
|
|
env->itlb_tag[i] & ~0x1fffULL,
|
|
env->itlb_tte[i] & 0x1ffffffe000ULL,
|
|
mask,
|
|
env->itlb_tte[i] & 0x4? "priv": "user",
|
|
env->itlb_tte[i] & 0x40? "locked": "unlocked",
|
|
env->itlb_tag[i] & 0x1fffULL);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif /* DEBUG_MMU */
|
|
|
|
#endif /* TARGET_SPARC64 */
|
|
#endif /* !CONFIG_USER_ONLY */
|
|
|
|
void memcpy32(target_ulong *dst, const target_ulong *src)
|
|
{
|
|
dst[0] = src[0];
|
|
dst[1] = src[1];
|
|
dst[2] = src[2];
|
|
dst[3] = src[3];
|
|
dst[4] = src[4];
|
|
dst[5] = src[5];
|
|
dst[6] = src[6];
|
|
dst[7] = src[7];
|
|
}
|